Datasheet

TUSB1310A
SLLSE32E NOVEMBER 2010REVISED JULY 2012
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4.2.2 Function Control (04h-06h)
Address: 04h-06h (Read), 04h (Write), 05h (Set), 06h (Clear)
Table 4-4. Function Control
BITS NAME ACCESS RESET DESCRIPTION
Selects the required transceiver speed 00b : Enable HS
transceiver
01b: Enable FS transceiver
1:0 XcvrSelect Rd/Wr/S/C 1h
10b: Enable LS transceiver
11b: Enable FS transceiver for LS packets
(FS preamble is automatically pre-pended)
Controls the internal 1.5-kΩ pullup resister and 45-Ω HS
terminations. Control over bus resistors changes depending
2 TermSelect Rd/Wr/S/C 0 on XcvrSelect, OpMode, DpPulldown and DmPulldown. Since
low speed peripherals never support full speed or hi-speed,
providing the 1.5 kΩ on DM for low speed is optional.
Selects the required bit encoding style during transmit
00 : Normal operation
01: Non-driving
4:3 OpMode Rd/Wr/S/C 00
10: Disable bit-stuff and NRZI encoding
11: Do not automatically add SYNC and EOP when
transmitting. Must be used only for HS packets.
Active High transceiver reset. After the Link sets this bit, the
TUSB1310A must assert the ULPI_DIR and reset the ULPI.
When the reset is completed, the PHY de-asserts the
ULPI_DIR and automatically clears this bit. After de-asserting
5 Reset Rd/Wr/S/C 0 the ULPI_DIR, the PHY must re-assert the ULPI_DIR and
send an RX CMD update on the Link Layer Controller. The
Link Layer Controller must wait for the ULPI_DIR to de-
assert before using the ULPI bus. Does not reset the ULPI or
ULPI register set.
Active low PHY suspend. Put the TUSB1310A into Low
Power Mode. The PHY can power down all blocks except the
full speed receiver, OTG com-parators, and the ULPI pins.
6 SuspendM Rd/Wr/S/C 1h The PHY must auto-matically set this bit to 1 when Low
Power Mode is exited.
0: Low Power Mode
1: Powered
7 Reserved Rd 0 Reserved
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