Datasheet

TUSB1310A
www.ti.com SLLSE32E –NOVEMBER 2010–REVISED JULY 2012
Contents
1 PRODUCT OVERVIEW ......................................................................................................... 6
1.1 Features ...................................................................................................................... 6
1.2 Target Applications ......................................................................................................... 6
1.3 Introduction .................................................................................................................. 7
1.4 Functional Block Diagram .................................................................................................. 7
2 PIN DESCRIPTIONS ............................................................................................................. 9
2.1 Configuration Pins .......................................................................................................... 9
2.2 PIPE .......................................................................................................................... 9
2.3 ULPI ......................................................................................................................... 12
2.3.1 ULPI Modes ..................................................................................................... 12
2.4 Clocking ..................................................................................................................... 13
2.5 JTAG Interface ............................................................................................................. 13
2.6 Reset and Output Control Interface ..................................................................................... 13
2.7 Strap Options .............................................................................................................. 13
2.8 USB Interfaces ............................................................................................................. 14
2.9 Special Connect ........................................................................................................... 14
2.10 Power and Ground ........................................................................................................ 15
3 FUNCTIONAL DESCRIPTION ............................................................................................... 17
3.1 Power On and Reset ...................................................................................................... 17
3.1.1 RESETN and PHY_RESETN – Hardware Reset .......................................................... 17
3.1.2 ULPI Reset – Software Reset ................................................................................. 17
3.1.3 OUT_ENABLE - Output Enable .............................................................................. 17
3.1.4 Power Up Sequence ........................................................................................... 17
3.2 Clocks ....................................................................................................................... 18
3.2.1 Clock Distribution ............................................................................................... 18
3.2.2 Output Clock .................................................................................................... 18
3.3 Power Management ....................................................................................................... 18
3.3.1 USB Power Management ...................................................................................... 19
3.4 Receiver Status ............................................................................................................ 20
3.4.1 Clock Tolerance Compensation .............................................................................. 20
3.4.2 Receiver Detection ............................................................................................. 20
3.4.3 8b/10b Decode Errors .......................................................................................... 21
3.4.4 Elastic Buffer Errors ............................................................................................ 21
3.4.5 Disparity Errors ................................................................................................. 21
3.5 Loopback ................................................................................................................... 21
3.6 Adaptive Equalizer ........................................................................................................ 22
4 REGISTERS ...................................................................................................................... 23
4.1 Register Definitions ....................................................................................................... 23
4.2 Register Map ............................................................................................................... 23
4.2.1 Vendor ID and Product ID (00h-03h) ........................................................................ 23
4.2.2 Function Control (04h-06h) .................................................................................... 24
4.2.3 Interface Control (07h-09h) .................................................................................... 25
4.2.4 OTG Control ..................................................................................................... 25
4.2.5 USB Interrupt Enable Rising (0Dh-0Fh) ..................................................................... 25
4.2.6 USB Interrupt Enable Falling (10h-12h) ..................................................................... 26
4.2.7 USB Interrupt Status (13h) .................................................................................... 26
4.2.8 USB Interrupt Latch (14h) ..................................................................................... 26
4.2.9 Debug (15h) ..................................................................................................... 26
4.2.10 Scratch Register (16-18h) ..................................................................................... 26
5 DESIGN GUIDELINES ......................................................................................................... 27
5.1 Chip Connection on PCB ................................................................................................. 27
2 Contents Copyright © 2010–2012, Texas Instruments Incorporated