TUSB1310A USB 3.0 Transceiver Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TUSB1310A www.ti.com SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 Contents 1 PRODUCT OVERVIEW 1.1 1.2 1.3 1.4 2 PIN DESCRIPTIONS 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 3 3.2 3.3 3.4 3.5 3.6 5 ............................................................................................... 17 17 17 17 17 17 18 18 18 18 19 20 20 20 21 21 21 21 22 ...................................................................................................................... 23 Register Definitions .........
TUSB1310A www.ti.com 5.2 6 SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 5.1.1 USB Connector Pins Connection ............................................................................. 5.1.2 Clock Connections .............................................................................................. Clock Source Requirements ............................................................................................. 5.2.1 Clock Source Selection Guide ................................................
TUSB1310A SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 www.ti.com List of Figures 1-1 Typical Application ................................................................................................................. 7 1-2 Functional Block Diagram 3-1 5-1 5-2 5-3 5-4 6-1 6-2 6-3 6-4 6-5 4 ........................................................................................................ Power-Up Sequence ........................................................................................
TUSB1310A www.ti.com SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 List of Tables 2-1 Configuration Pins ................................................................................................................. 9 2-2 PIPE Signal Description........................................................................................................... 9 2-3 ULPI Signal Description .........................................................................................................
TUSB1310A SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 www.ti.com USB 3.0 Transceiver Check for Samples: TUSB1310A 1 PRODUCT OVERVIEW 1.1 Features • Universal Serial Bus (USB) – Single Port 5.0-Gbps USB 3.0 Physical Layer Transceiver • One 5.0-Gbps SuperSpeed Connection • One 480-Mbps HS/FS/LS Connection – Fully Compliant with USB 3.0 Specification, Revision 1.0 – Supports 3+ Meters USB 3.
TUSB1310A www.ti.com 1.3 SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 Introduction The TUSB1310A is a single port, 5.0-Gbps USB 3.0 physical layer transceiver operating off of a single reference clock provided by either a crystal or an external reference clock. The reference clock frequencies are selectable from 20, 25, 30, and 40 MHz. The TUSB1310A provides the clock to the USB controller. The use of a single reference clock allows the TUSB1310A to provide a cost effective USB 3.
TUSB1310A SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 www.ti.com Figure 1-2.
TUSB1310A www.ti.com 2 SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 PIN DESCRIPTIONS TYPE DESCRIPTION I Input O Output I/O Input/output PD, PU 2.1 Internal pull-down / pull-up S Strapping pin P Power Supply G Ground Configuration Pins The configuration pins are not latched by RESETN. Table 2-1. Configuration Pins SIGNAL NAME TYPE PIN NO. MODE NAME PHY_MODE1 I, PD H12 USB Must be set to 0. Operates as USB 3.0 transceiver. PHY_MODE0 I, PU J12 USB Must be set to 1.
TUSB1310A SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 www.ti.com Table 2-2. PIPE Signal Description (continued) SIGNAL NAME TYPE BALL NO. RX_DATA15 B9 RX_DATA14 A9 RX_DATA13 A8 RX_DATA12 B8 RX_DATA11 B5 RX_DATA10 B4 RX_DATA9 A4 RX_DATA8 RX_DATA7 O B3 A3 RX_DATA6 A2 RX_DATA5 B1 RX_DATA4 C2 RX_DATA3 C1 RX_DATA2 D1 RX_DATA1 D2 RX_DATA0 E2 RX_DATAK1 RX_DATAK0 RX_VALID B7 O O DESCRIPTION Parallel USB SuperSpeed data output bus.
TUSB1310A www.ti.com SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 Table 2-2. PIPE Signal Description (continued) SIGNAL NAME TYPE BALL NO. DESCRIPTION Active High. Used to communicate completion of several PHY functions including power management state transitions, rate change, and receiver detection. When this signal transitions during entry and exit from P3 and PCLK is not running, then the signaling is asynchronous.
TUSB1310A SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 2.3 www.ti.com ULPI The ULPI (ultra low pin count interface) is a low pin count USB PHY to a link layer controller interface. The ULPI consists of the interface and the ULPI registers. The TUSB1310A is always the master of the ULPI bus. Table 2-3. ULPI Signal Description SIGNAL NAME ULPI_CLK TYPE O ULPI_DATA7 BALL NO. DESCRIPTION P11 60-MHz interface clock. All ULPI signals are synchronous to ULPI_CLK.
TUSB1310A www.ti.com 2.4 SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 Clocking Table 2-5. Clock Signal Name Description SIGNAL NAME TYPE DESCRIPTION A12 Crystal Input. This pin is the clock reference input for the TUSB1310A. The TUSB1310A supports either a crystal unit, or a 1.8-V clock input. Frequencies supported are 20, 25, 30, or 40 MHz. O A11 Crystal output. If a 1.8-V clock input is connected to XI, XO must be left open. O D10 OOBCLK is driven in U3 mode. XI I XO CLKOUT 2.5 BALL NO.
TUSB1310A SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 www.ti.com Table 2-8. Strapping Options (continued) SIGNAL NAME ISO_START (ULPI_DATA7) TYPE S, I/O, PD BALL NO. DESCRIPTION N6 Active High. Puts PIPE into isolate mode. When in the isolate mode, TUSB1310A does not respond to packet data present at TX_DATA15-0, TXDATAK1-0 inputs and presents a high impedance on the PCLK, RX_DATA15-0, RX_DATAK1-0, RX_VALID outputs. When in the isolate mode, the TUSB1310A will continue to respond to ULPI.
TUSB1310A www.ti.com SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 2.10 Power and Ground Table 2-11. Power/Ground Signal Descriptions SIGNAL NAME TYPE BALL NO. VDDA3P3 P P12 VDDA1P8 P DESCRIPTION Analog 3.3-V power supply N14 A13 Analog 1.8-V power supply C10 C12 K14 VDDA1P1 G13 P Analog 1.1-V power supply G14 D14 C11 VDD1P8 VDD1P1 P P B2 C3 D4 D7 D8 D9 E4 F4 G4 H4 L5 L4 M3 L7 L8 L9 A5 A10 B6 B10 E1 F2 K2 L1 N5 P4 N10 P10 K13 D13 Digital IO 1.
TUSB1310A SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 www.ti.com Table 2-11. Power/Ground Signal Descriptions (continued) SIGNAL NAME TYPE BALL NO.
TUSB1310A www.ti.com SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 3 FUNCTIONAL DESCRIPTION 3.1 Power On and Reset The TUSB1310A has two hardware reset pins, a chip reset RESETN and a logic reset PHY_RESETN. The RESETN is used only at Power On. The PHY_RESETN can be used as a functional reset. The ULPI register also has a software reset. Until all power sources are supplied, the OUT_ENABLE pin can control the output driver enable.
TUSB1310A SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 www.ti.com Power Supplies XI RESETN Internal latched strapping pin states Latched data Internal resetn/ PLL_EN/SUSPENDM PCLK ULPI_CLK PHY_STATUS/ ULPI_DIR 300 µs Figure 3-1. Power-Up Sequence After proper power supply sequencing, the reference clock on XI starts to operate. On the RESETN deassertion, REFCLKSEL1-0 is determined depending on the PHY_MODE pins, PLL is locked and the valid ULPI_CLK and the valid PCLK are driven.
TUSB1310A www.ti.com 3.3.1 SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 USB Power Management The USB 3.0 specification improves power consumption by defining 4 power states, U0, U1, U2, and U3 while the PIPE specification defines P0, P1, P2 and P3. The POWER_DOWN pin states are mapped to LTSSM states as described in Table 3-2.
TUSB1310A SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 3.4 www.ti.com Receiver Status The TUSB1310A has an elastic buffer for clock tolerance compensation, the Link Partner detection, and some received data error detections. The receive data status from SSRXP/SSRXN differential pair presents on RX_STATUS2-0. If an error occurs during a SKP ordered-set, the error signaling has precedence. If more than one error occurs on a received byte, the errors have the priority below. 1. 8B/10B decode error 2.
TUSB1310A www.ti.com 3.4.3 SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 8b/10b Decode Errors When the TUSB1310A detects an 8b/10b decode error, it will assert a SUB symbol in the data on the RX_DATA where the bad byte occurred. In the same clock cycle that the SUB symbol is asserted on the RX_DATA, the 8b/10b decode error code (100b) will be asserted on the RX_STATUS.
TUSB1310A SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 3.6 www.ti.com Adaptive Equalizer The adaptive equalizer dynamically adjusts the forward gain and peaking of the analog equalizer to minimize the jitter at the cross over point of the eye diagram. This allows for greater jitter tolerance in the RX.
TUSB1310A www.ti.com SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 4 REGISTERS 4.1 Register Definitions Table 4-1. Register Definitions ACCESS CODE EXPANDED NAME Rd Read Register can be read. Read-only if this is the only mode given. Wr Write Pattern on the data bus will be written over all bits of the register. S Set Pattern on the data bus is OR’s with and written into the register. C Clear 4.2 DESCRIPTION Pattern on the data bus is a mask.
TUSB1310A SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 4.2.2 www.ti.com Function Control (04h-06h) Address: 04h-06h (Read), 04h (Write), 05h (Set), 06h (Clear) Table 4-4.
TUSB1310A www.ti.com 4.2.3 SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 Interface Control (07h-09h) Address: 07-09h (Read), 07h (Write), 08h (Set), 09h (Clear) Table 4-5. Interface Control BITS NAME ACCESS RESET 0 Reserved Rd 0b Reserved, only write a 0 to this bit. DESCRIPTION 1 Reserved Rd 0b Reserved, only write a 0 to this bit. 2 Reserved Rd 0h Reserved 3 ClockSuspendM Rd/Wr/S/C 0b Active low clock suspend. Valid only in Serial Mode.
TUSB1310A SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 4.2.6 www.ti.com USB Interrupt Enable Falling (10h-12h) Address: 10-12h (Read), 10h (Write), 11h (Set), 12h (Clear) Table 4-8. USB Interrupt Enable Falling BITS 0 NAME Hostdisconnect Fall 4.2.7 ACCESS Rd/Wr/S/C RESET DESCRIPTION 1b Generate an interrupt event notification when Host-disconnect changes from high to low. Applicable only in host. USB Interrupt Status (13h) Address: 13h (Read-only) Table 4-9.
TUSB1310A www.ti.com SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 5 DESIGN GUIDELINES 5.1 Chip Connection on PCB Components should be placed close to the TUSB1310A to reduce the trace length of the interface between the components and the TUSB1310A. If external capacitors can not accommodate a close placement, shielding to ground is recommended. SSTXN SSTXP SSRXN SSRXP USB Connector DP DM VBUS 90.
TUSB1310A SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 www.ti.com 90.9 kW ±1% 10 kW ±1% Figure 5-2. USB Standard-A Connector Pin Connection 90.9 kW ±1% 10 kW ±1% Figure 5-3. USB Standard-B Connector Pin Connection 5.1.2 Clock Connections The TUSB1310A supports an external oscillator source or a crystal unit. If a clock is provided to XI instead of a crystal, XO is left open. Otherwise, if a crystal is used, the connection needs to follow the guidelines below.
TUSB1310A www.ti.com SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 Load capacitance (CLOAD) of the crystal varying with the crystal vendors is the total capacitance value of the entire oscillation circuit system as seen from the crystal. It includes two external capacitors CL1 and CL2 in Figure 5-4. The trace length between the decoupling capacitors and the corresponding power pins on the TUSB1310A needs to be minimized.
TUSB1310A SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 www.ti.com Table 5-1. Oscillator Specification (continued) PARAMETER MIN TYP MAX UNITS Reference clock TJ with JTF (total p-p) (2) (3) 25 psec Reference clock jitter (absolute p-p) (4) 50 psec (3) (4) CONDITION Calculated as 14.1 x RJ + DJ Absolute phase jitter (p-p) 5.2.3 Crystal Either a 20-MHz, 25-MHz, 30-MHz, or 40-MHz crystal can be selected. A parallel, 20-pF load crystal should be used if a crystal source is used. Table 5-2.
TUSB1310A www.ti.com SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 6 ELECTRICAL SPECIFICATIONS 6.1 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) VALUE UNIT VDD1P1 steady-state supply voltage –0.3 to 1.4 V VDD1P8 steady-state supply voltage –0.3 to 2.45 V VDDA1P1 steady-state supply voltage –0.3 to 1.4 V VDDA1P8 steady-state supply voltage –0.3 to 2.45 V VDDA3P3 steady-state supply voltage –0.3 to 3.8 V 6.
TUSB1310A SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 www.ti.com DC CHARACTERISTICS for 1.
TUSB1310A www.ti.com SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 VDD1P8 and Analog Power Supplies XI OUT_ENABLE ULPI_DIR VDD1P1 Tcfgin1 RESETN Latch-In of Hardware Strapping Pins Tcfgin2 Drive Output Strapping pins Figure 6-1. Power Up and Reset Timing Table 6-1.
TUSB1310A SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 6.5.3 www.ti.com PIPE Receive Tcyc3 PCLK Tdly3 RX_DATA15-0 RX_DATAK1-0 RX_VALID RX_STATUS2-0 PHY_STATUS Valid Data Figure 6-3. PIPE Receive Timing Table 6-3.
TUSB1310A www.ti.com SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 Table 6-5. ULPI Clock Parameters (continued) DESCRIPTION SYMBOL Rise and fall time 6.5.6 MIN TYP MAX UNITS Trise/Tfall ns ULPI Transmit ULPI_CLK Tsc8 Thc8 Tsd8 Thd8 ULPI_STP Valid Data ULPI_DATA7-0 In (8-bit) Tsdd8 Thdd8 Tsdd8 Thdd8 Figure 6-4. ULPI Transmit Timing Table 6-6. ULPI Transmit Timing DESCRIPTION SYMBOL ULPI_STP setup time Tsc8, Tsd8 ULPI_STP hold time Thc8, Thd8 6.5.
TUSB1310A SLLSE32E – NOVEMBER 2010 – REVISED JULY 2012 6.5.8 www.ti.com Power State Transition Time The P1 to P0 transition time is the amount of time for the TUSB1310A to return to P0 state, after having been in the P1 state. This time is measured from when the MAC sets the POWER_DOWN signals to P0 until the TUSB1310A asserts PHY_STATUS. The TUSB1310A asserts PHY_STATUS when it is ready to begin data transmission and reception.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE MATERIALS INFORMATION www.ti.com 2-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TUSB1310AZAYR Package Package Pins Type Drawing NFBGA ZAY 175 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 12.35 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 12.35 2.3 16.0 24.
PACKAGE MATERIALS INFORMATION www.ti.com 2-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TUSB1310AZAYR NFBGA ZAY 175 1000 336.6 336.6 41.
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