Datasheet

TUSB1211
www.ti.com SLLSE80A –MARCH 2011– REVISED JANUARY 2012
Standalone USB Transceiver Chip
Check for Samples: TUSB1211
1 Features
1
• USB2.0 PHY Transceiver Chip, Designed to • Can be Interfaced to Peripheral, Host or OTG
Interface With a USB Controller via a ULPI Controller Devices via ULPI. Suited to Portable
Interface, Fully Compliant With: Devices or System ASICs with Built-In
Controller Core.
– Universal Serial Bus Specification Rev. 2.0
• Complete HS-USB Physical Front-End:
– On-The-Go Supplement to the USB 2.0
Specification Rev. 1.3 – Supports High Speed (480 Mbit/s), Full
Speed (12 Mbit/s) and Low Speed (1.5 Mbit/s)
– UTMI+ Low Pin Interface (ULPI) Specification
Rev. 1.1 – Integrated Phase-Locked Loop (PLL)
Supporting 2 Clock Frequencies 19.2 MHz/26
– ULPI 12-Pin SDR Interface
MHz
– USB Battery Charging Specification Rev. 1.1
– Integrated 45 Ω ±10% High-Speed
• USB Battery Charger Detection Feature
Termination Resistors, 1.5 kΩ Full-Speed
– Detection Compliant to USB Charging
Device Pullup Resistor, 15 kΩ Host
Specification v1.1 Including ACA Detection
Termination Resistors
– Additional DP Weak Pullup Resistor
– Integrated Transmit and Receive Paths for
Available for Detection of DP/DM
Parallel-to-Serial and Serial-to-Parallel Data
Connectivity
Conversion
• DP/DM Line External Component
– USB Data Recovery to Allow Recovery of
Compensation (TI Patent Pending)
USB Data up to ±500 ppm Frequency Drift
• Complete USB OTG Physical Front-End that
– Bit-Stuffing Insertion During Transmit and
Supports Host Negotiation Protocol (HNP) and
Removal During Receive
Session Request Protocol (SRP)
– Non-Return-to-Zero Inverted (NRZI)
• V
BUS
Overvoltage Protection Circuitry Protects
Encoding and Decoding
V
BUS
Pin in Range –2 V to 20 V
– Supports Bus Reset, Suspend, Resume and
• Internal 5 V Short-Circuit Protection of DP, DM,
High-Speed Detection Handshake (Chirp)
and ID Pins for Cable Shorting to V
BUS
Pin
– HS USB DP/DM Impedance Programmability
• ULPI Interface:
for External Component Compensation
– I/O Interface (1.8V) Optimized for
• OTG Ver1.3:
Non-Terminated 50 Ω Line Impedance
– Control of External V
BUS
Switch or Charge
– ULPI CLOCK Pin (60 MHz) Supports Both
Pump
Input and Output Clock Configurations
– V
BUS
Fault Detection
– Fully Programmable ULPI-Compliant
– Both Session Request Protocol (SRP)
Register Set
Methods Supported: Data Pulsing and V
BUS
• Full Industrial Grade Operating Temperature
Pulsing
Range from –40°C to 85°C
– Integrated V
BUS
Detectors and Cable
• Available in a TFBGA36 Ball Package
Detection (ID)
• USB HS Start-Of-Frame Clock Output Feature
• Internal Power-On Reset (POR) Circuit
Available on SOF Pin Can be Used to
• Flexible System Integration and Very Low
Synchronize Another Application, e.g., Audio,
Current Consumption, Optimized for Portable
With the USB Packet Stream
Devices
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to
Copyright © 2011–2012, Texas Instruments Incorporated
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.