Datasheet

TUSB1211

SLLSE80A –MARCH 2011– REVISED JANUARY 2012

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7 USB Transceiver (PHY)

The TUSB1211 device includes a universal serial bus (USB) on-the-go (OTG) transceiver that supports

USB 480 Mb/s high-speed (HS), 12 Mb/s full-speed (FS), and USB 1.5 Mb/s low-speed (LS) through a

12-pin UTMI+ low pin interface (ULPI).

NOTE

LS device mode is not allowed by a USB2.0 HS capable PHY, therefore it is not supported

by TUSB1211. This is clearly stated in USB2.0 standard Chapter 7, page 119, second

paragraph: “A high-speed capable upstream facing transceiver must not support low-speed

signaling mode..” There is also some related commentary in Chapter 7.1.2.3.

Table 7-1. Interface Target Frequencies

IO INTERFACE INTERFACE DESIGNATION TARGET FREQUENCY

High speed 480 Mbits/s

USB Universal serial bus Full speed 12 Mbits/s

Low speed 1.5 Mbits/s

7.1 PHY Overview

The PHY is the physical signaling layer of the USB 2.0. It essentially contains all the drivers and receivers

required for physical data and protocol signaling on the DP and DM lines.

The PHY interfaces to the USB controller through a standard 12-pin digital interface called UTMI+ low pin

interface (ULPI).

The transmitters and receivers inside the PHY are classified into two main classes.

• The full-speed (FS) and low-speed (LS) transceivers. These are the legacy USB1.x transceivers.

• The HS (HS) transceivers

In order to bias the transistors and run the logic, the PHY also contains reference generation circuitry

which consists of:

• A PLL which does a frequency multiplication to achieve the 480-MHz low-jitter clock necessary for

USB and also the clock required for the switched capacitor resistance block.

• Internal biasing circuitry

Built-in pullup and pulldown resistors are used as part of the protocol signaling.

Apart from this, the PHY also contains circuitry which protects it from accidental short on the DP and DM

lines to 5 V or GND.

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Product Folder Link(s): TUSB1211