Datasheet

TUSB1211
www.ti.com SLLSE80A –MARCH 2011– REVISED JANUARY 2012
register map in ULPI specification Rev1.1.
This is the case because OTG_CONTROL register bits DRVVBUS and DRVVBUSEXTERNAL bits are
0 by default, and DPPULLDOWN, DMPULLDOWN bits are 1 by default such that the 15 kΩ pulldown
resistors at DP/DM pins are enabled by default.
It is the responsibility of the link to enable external VBUS supply if required in Host mode, or to
reconfigure the PHY if required in Device mode.
• Hardware charger detection power-up
When the chip is not selected (CS=0 or CS_N=1), but VBUS is present and CHRG_EN_N pin is at
GND, and VBAT > VBAT_MNTR then TUSB1211 will power-up in Hardware Charger Detection Mode.
Power resources will be configured sequentially until the device reaches the power state USBON .
However since chip is not selected, internal power-on-reset signal PORZ will be not be released and
USB PLL will not start up. Instead the device will enter USB Battery charger finite state machine
(FSM) .
Copyright © 2011–2012, Texas Instruments Incorporated Power Management 15
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Product Folder Link(s): TUSB1211