Datasheet

TUSB1211
SLLSE80A –MARCH 2011– REVISED JANUARY 2012 www.ti.com
5 Clock System
5.1 USB PLL Reference Clock
The USB PLL block generates the clocks used to synchronize:
• the ULPI interface (60 MHz clock)
• the USB interface (depending on the USB data rate, 480 Mbps, 12 Mbps or 1.5 Mbps)
TUSB1211 requires an external reference clock which is used as an input to the 480MHz USB PLL block.
Depending on the clock configuration, this reference clock can be provided either at REFCLK pin or at
CLOCK pin.
By default CLOCK pin is configured as an input.
Two clock configurations are possible:
• Input clock configuration (see Section 5.1.1)
• Output clock configuration (see Section 5.1.1)
5.1.1 ULPI Input Clock Configuration
In this mode REFCLK must be externally tied to GND.
CLOCK remains configured as an input.
When the ULPI interface is used in “input clock configuration”, i.e., the 60 MHz ULPI clock is provided to
TUSB1211 on CLOCK pin, then this is used as the reference clock for the 480 MHz USB PLL block.
Table 5-1. Electrical Characteristics: CLOCK Input
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CLOCK input duty cycle 40 60 %
F
CLOCK
CLOCK nominal frequency 60 MHz
CLOCK input rise/fall time In % of CLOCK period T
CLOCK
( = 1/F
CLOCK
) 10 %
CLOCK input frequency accuracy 250 ppm
CLOCK input integrated jitter 600 ps rms
5.1.2 ULPI Output Clock Configuration
In this mode a reference clock must be externally provided on REFCLK pin.
When an input clock is detected on REFCLK pin then CLOCK will automatically change to an output, i.e.,
60 MHz ULPI clock is output by TUSB1211 on CLOCK pin.
Two reference clock input frequencies are supported. REFCLK input frequency is communicated to
TUSB1211 via a configuration pin, CFG, see F
REFCLK
in Table 5-2 for frequency correspondence.
TUSB1211 supports square-wave reference clock input only.
Table 5-2. Electrical Characteristics: REFCLK
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REFCLK input duty cycle 40 60 %
FREFCLK REFCLK nominal frequency When CFG pin is tied to GND 19.2
MHz
When CFG pin is tied to V
DDIO
26
REFCLK input rise/fall time In % of REFCLK period T
REFCLK
( = 1/F
REFCLK
) 20 %
REFCLK input freq accuracy 250 ppm
REFCLK input integrated jitter 600 ps rms
12 Clock System Copyright © 2011–2012, Texas Instruments Incorporated
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