Datasheet

Link
Controller
A3
A2
A1
B1
TUSB1211
C
BYP
R
CDETPUOD
C
VDDIO
V Supply
BAT
V Supply
BAT
V
DDIO
Supply
DATA0
DATA1
DATA2
DATA3
DATA0
DATA1
DATA2
DATA3
C6
B6
A6
A5
DATA4
DATA5
DATA6
DATA7
DATA4
DATA5
DATA6
DATA7
A4
E5
DIR
CLOCK
DIR
CLOCK
D6
D5
NXT
STP
NXT
STP
D4
E2
FAULT
EN
OUT
FAULT
PSW
D1
C1
D3
F4
V
BUS
ID
ID
DM
DP
B3
C4
F5
F6
C3
(B)
(D)
(E)
( )
D
C
(A)
(A)
SOF
CS_N
REFCLK
RESET_N
cS
SOF
REFCLK
RESET_N
CS
F3
B5
B2
V
DDIO
V
DDIO
V
BAT
C2
NC
C
VDD15
C
VDD33
B4
E3
REG3V3
CFG
E6
REG1V5
E1
F1
CHRG_POL
CHRG_EN_N
F2
CHRG_DET
To Charger
C5
D2
GND
GND
E4
GND
V
BUS
USB Receptacle
No Connection
V
BUS
Supply
ESD
TPD4S012
GND
DP
DM
SHIELD
TUSB1211
www.ti.com SLLSE80A –MARCH 2011– REVISED JANUARY 2012
4 Application Diagram
Figure 4-1 shows the suggested application diagram (Host or OTG, ULPI output-clock mode)
A. Optional: SOF (open if unused); RESET_N (tie to V
DDIO
if unused)
B. Link controls chip select via CS pin with CS_N at GND. ALternatively, Link may control CS_N pin with CS pin tied to
V
DDIO
.
C. CHRG_DET is active-low (tie CHRG_POL to V
BAT
for CHRG_DET active high).
D. Dead battery charger detection is enabled (tie CHRG_EN_N to V
BAT
to disable).
E. CFG tied to V
DDIO
for 26 MHz input at REFCLK (tie to GND for 19.2 MHz).
Figure 4-1. USB-OTG with ULPI Output Clock
Copyright © 2011–2012, Texas Instruments Incorporated Application Diagram 11
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Product Folder Link(s): TUSB1211