Datasheet
V
DDIO
DIR
V
DD18
STP
V
DD18
RESETB
CLOCK
N/C
32
31
30
29
28
27
26
25
REFCLK 1
24
N/C
NXT 2
23
ID
DATA0 3 TUSB1210
RHB PACKAGE
(TOP VIEW)
22
V
BUS
DATA1 4 32-pin QFN
21
V
BAT
DATA2 5
20
V
DD33
DATA3 6
19
DM
DATA4 7
GND
18
DP
N/C 8
17
CPEN
9
10
11
12
13
14
15
16
DATA5
DATA6
CS
V
DD15
DATA7
CFG
N/C
N/C
TUSB1210
www.ti.com
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
2 Description
The TUSB1210 is a USB2.0 transceiver chip, designed to interface with a USB controller via a ULPI
interface. It supports all USB2.0 data rates (High-Speed 480Mbps, Full-Speed 12 Mbps and Low-Speed
1.5Mbps), and is compliant to both Host and Peripheral modes. It additionally supports a UART mode and
legacy ULPI serial modes.
TUSB1210 also supports the OTG (Ver1.3) optional addendum to the USB 2.0 Specification, including
Host Negotiation Protocol (HNP) and Session Request Protocol (SRP).
TUSB1210 is optimized to be interfaced through a 12-pin SDR UTMI Low Pin Interface (ULPI), supporting
both input clock and output clock modes, with 1.8 V interface supply voltage.
TUSB1210 integrates a 3.3 V LDO, which makes it flexible to work with either battery operated systems or
pure 3.3 V supplied systems. Both the main supply and the 3.3 V power domain can be supplied through
an external switched-mode converter for optimized power efficiency.
TUSB1210 includes a POR circuit to detect supply presence on V
BAT
and V
DDIO
pins. TUSB1210 can be
disabled or configured in low power mode for energy saving.
TUSB1210 is protected against accidental shorts to 5 V or ground on its exposed interface (DP/DM/ID). It
is also protected against up to 20 V surges on V
BUS
.
TUSB1210 integrates a high-performance low-jitter 480 MHz PLL and supports two clock configurations.
Depending on the required link configuration, TUSB1210 supports both ULPI input and output clock
mode : input clock mode, in which case a square-wave 60 MHz clock is provided to TUSB1210 at the
ULPI interface CLOCK pin; and output clock mode in which case TUSB1210 can accept a square-wave
reference clock at REFCLK of either 19.2 MHz, 26 MHz. Frequency is indicated to TUSB1210 via the
configuration pin CFG. This can be useful if a reference clock is already available in the system.
1
2.1 Terminal Description
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to
Copyright © 2009–2012, Texas Instruments Incorporated
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.