Datasheet

TUSB1210
www.ti.com SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
4 Clock System
4.1 USB PLL Reference Clock
The USB PLL block generates the clocks used to synchronize :
• the ULPI interface (60 MHz clock)
• the USB interface (depending on the USB data rate, 480 Mbps, 12 Mbps or 1.5 Mbps)
TUSB1210 requires an external reference clock which is used as an input to the 480 MHz USB PLL block.
Depending on the clock configuration, this reference clock can be provided either at REFCLK pin or at
CLOCK pin. By default CLK pin is configured as an input.
Two clock configurations are possible:
• Input clock configuration (see Section 4.2)
• Output clock configuration (see Section 4.3)
4.2 ULPI Input Clock Configuration
In this mode REFCLK must be externally tied to GND. CLOCK remains configured as an input.
When the ULPI interface is used in “input clock configuration”, i.e., the 60 MHz ULPI clock is provided to
TUSB1210 on Clock pin, then this is used as the reference clock for the 480 MHz USB PLL block.
Table 4-1. Electrical Characteristics: Clock Input
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Clock input duty cycle 40 60 %
f
CLK
Clock nominal frequency 60 MHz
Clock input rise/fall time In % of clock period t
CLK
( = 1/f
CLK
) 10 %
Clock input frequency accuracy 250 ppm
Clock input integrated jitter 600 ps rms
4.3 ULPI Output Clock Configuration
In this mode a reference clock must be externally provided on REFCLK pin When an input clock is
detected on REFCLK pin then CLK will automatically change to an output, i.e., 60 MHz ULPI clock is
output by TUSB1210 on CLK pin.
Two reference clock input frequencies are supported. REFCLK input frequency is communicated to
TUSB1210 via a configuration pin, CFG, see f
REFCLK
in Table 8-1 for frequency correspondence.
TUSB1210 supports square-wave reference clock input only. Reference clock input must be square-wave
of amplitude in the range 3.0 V to 3.6 V.
Table 4-2. Electrical Characteristics: REFCLK
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REFCLK input duty cycle 40 60 %
When CFG pin is tied to GND 19.2
f
REFCLK
REFCLK nominal frequency MHz
When CFG pin is tied to V
DDIO
26
In % of clock period t
REFCLK
( =
REFCLK input rise/fall time 20 %
1/f
REFCLK
)
REFCLK input frequency accuracy 250 ppm
REFCLK input integrated jitter 600 ps rms
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