Datasheet

TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012 www.ti.com
Table 2-1. Terminal Functions
TERMINAL
A/D TYPE LEVEL DESCRIPTION
NO. NAME
V
DD33
Reference clock input (square-wave only). Tie to GND when pin 26
(CLOCK) is required to be Input mode. Connect to square-wave reference
1 REFCLK A I 3.3 V clock of amplitude in the range of 3 V to 3.6 V when Pin 26 (CLOCK) is
required to be Output mode. See pin 14 (CFG) description for REFCLK
input frequency settings.
2 NXT D O V
DDIO
ULPI NXT output signal
3 DATA0 D I/O V
DDIO
ULPI DATA input/output signal 0 synchronized to CLOCK
4 DATA1 D I/O V
DDIO
ULPI DATA input/output signal 1 synchronized to CLOCK
5 DATA2 D I/O V
DDIO
ULPI DATA input/output signal 2 synchronized to CLOCK
6 DATA3 D I/O V
DDIO
ULPI DATA input/output signal 3 synchronized to CLOCK
7 DATA4 D I/O V
DDIO
ULPI DATA input/output signal 4 synchronized to CLOCK
8 N/C – – V
DDIO
No connect
9 DATA5 D I/O V
DDIO
ULPI DATA input/output signal 5 synchronized to CLOCK
10 DATA6 D I/O V
DDIO
ULPI DATA input/output signal 6 synchronized to CLOCK
Active-high chip select pin. When low the IC is in power down and ULPI
11 CS D I V
DDIO
bus is tri-stated. When high normal operation. Tie to V
DDIO
if unused.
12 VDD15 A power 1.5-V internal LDO output. Connect to external filtering capacitor.
13 DATA7 D I/O V
DDIO
ULPI DATA input/output signal 7 synchronized to CLOCK
REFCLK clock frequency configuration pin. Two frequencies are
14 CFG D I V
DDIO
supported: 19.2 MHz when 0, or 26 MHz when 1.
15 N/C – – – No connect
16 N/C – – – No connect
17 CPEN D O V
DD33
CMOS active-high digital output control of external 5V VBUS supply
18 DP A I/O V
DD33
DP pin of the USB connector
19 DM A I/O V
DD33
DM pin of the USB connector
20 V
DD33
A power V
DD33
3.3-V internal LDO output. Connect to external filtering capacitor.
21 V
BAT
A power V
BAT
Input supply voltage or battery source
22 V
BUS
A power V
BUS
V
BUS
pin of the USB connector
23 ID A I/O V
DD33
Identification (ID) pin of the USB connector
24 N/C – – – No connect
25 N/C – – – No connect
ULPI 60 MHz clock on which ULPI data is synchronized.
Two modes are possible:
26 CLOCK D O V
DDIO
Input Mode: CLOCK defaults as an input.
Output Mode: When an input clock is detected on REFCLK pin (after 4
rising edges) then CLOCK will change to an output.
When low, all digital logic (except 32 kHz logic required for power up
27 RESETB D I V
DDIO
sequencing) including registers are reset to their default values, and ULPI
bus is tri-stated. When high, normal USB operation.
28 V
DD18
A power V
DD18
External 1.8-V supply input. Connect to external filtering capacitor.
29 STP D I V
DDIO
ULPI STP input signal
30 V
DD18
A power V
DD18
External 1.8-V supply input. Connect to external filtering capacitor.
31 DIR D O V
DDIO
ULPI DIR output signal
External 1.8V supply input for digital I/Os. Connect to external filtering
32 V
DDIO
A I V
DDIO
capacitor.
8 Description Copyright © 2009–2012, Texas Instruments Incorporated
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