Datasheet

TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012 www.ti.com
Standalone USB Transceiver Chip Silicon
Check for Samples: TUSB1210
1 Features
Controller Core.
• USB2.0 PHY Transceiver Chip, Designed to
Interface With a USB Controller via a ULPI • Complete HS-USB Physical Front-End:
Interface, Fully Compliant With:
– Supports High Speed (480 Mbit/s), Full
– Universal Serial Bus Specification Rev. 2.0 Speed (12 Mbit/s) and Low Speed (1.5 Mbit/s)
– On-The-Go Supplement to the USB 2.0 – Integrated Phase-Locked Loop (PLL)
Specification Rev. 1.3 Supporting 2 Clock Frequencies 19.2 MHz/26
MHz
– UTMI+ Low Pin Interface (ULPI) Specification
Rev. 1.1 – Integrated 45 Ω ±10% High-Speed
Termination Resistors, 1.5 kΩ Full-Speed
– ULPI 12-pin SDR Interface
Device Pull-up Resistor, 15 kΩ Host
• DP/DM Line External Component
Termination Resistors
Compensation (TI Patent Pending)
– Integrated Transmit and Receive Paths for
• Interfaces to Host, Peripheral and OTG Device
Parallel-to-Serial and Serial-to-Parallel Data
Cores; Optimized for Portable Devices or
Conversion
System ASICs with Built-in USB OTG Device
– USB Data Recovery to Allow Recovery of
Core
USB Data up to ±500 ppm Frequency Drift
• Complete USB OTG Physical Front-End that
– Bit-Stuffing Insertion During Transmit and
Supports Host Negotiation Protocol (HNP) and
Removal During Receive
Session Request Protocol (SRP)
– Non-Return-to-Zero Inverted (NRZI)
• V
BUS
Overvoltage Protection Circuitry Protects
Encoding and Decoding
V
BUS
Pin in Range –2 V to 20 V
– Supports Bus Reset, Suspend, Resume and
• Internal 5 V Short-Circuit Protection of DP, DM,
High-Speed Detection Handshake (Chirp)
and ID Pins for Cable Shorting to V
BUS
Pin
– HS USB DP/DM Impedance Programmability
• ULPI Interface:
for External Component Compensation
– I/O Interface (1.8V) Optimized for Non-
• OTG Ver1.3 :
Terminated 50 Ω Line Impedance
– Control of External V
BUS
Switch or Charge
– ULPI CLOCK Pin (60 MHz) Supports Both
Pump
Input and Output Clock Configurations
– Both Session Request Protocol (SRP)
– Fully Programmable ULPI-Compliant
Methods Supported: Data Pulsing and V
BUS
Register Set
Pulsing
• Full Industrial Grade Operating Temperature
– Integrated V
BUS
Detectors and Cable
Range from –40°C to 85°C
Detection (ID)
• Available in a 32-Pin Quad Flat No Lead [QFN
• Internal Power-On Reset (POR) Circuit
(RHB)] Package
• Flexible System Integration and Very Low
• Can Be Interfaced to Peripheral, Host or OTG
Current Consumption, Optimized for Portable
Controller Devices via ULPI. Suited to Portable
Devices
Devices or System ASICs with Built-In
6 Features Copyright © 2009–2012, Texas Instruments Incorporated