Datasheet

(See Note A)
(See Note C)
(See Note B)
(See Note E)
(See Note D)
TUSB1210
Link Controller
V
DDIO
V
BUS
V
BUS
V
BAT
V
DD33
C
VDD18
C
VDDIO
C
BYP
C
VDD33
C
VDD15
C
VBUS
V
DD18
V
DD15
7
27
5
13
12
17
4
10
USB Receptacle
ESD
3
9
29
6
2
GND
GND
1.8-V Supply
V
DDIO
Supply
3.1 5.5 V–
Supply
V
DDIO
Supply
CPEN
CS_OUT
STP
RESETB
REFCLK
CLOCK
NXT
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
STP
RESETB
REFCLK
NXT
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
20
21
22
26
32
28, 30
31
DIR
DIR
1
CLKIN
14
11
CS
CFG
18
23
19
DP
DM
ID
DP
DM
SHIELD
N/C
25
N/C
24
N/C
16
N/C
15
N/C
8
TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012 www.ti.com
A. Pin 11 (CS) : can be tied high to V
IO
if CS_OUT pin unavailable; Pin 14 (CFG) : Tied to V
DDIO
for 26MHz REFCLK
mode here, tie to GND for 19.2MHz mode.
B. Pin 1 (REFCLK) : connect to external 3.3V square-wave reference clock
C. Ext 3 V supply supported
D. Pin 27 (RESETB) can be tied to V
DDIO
if unused.
E. Pins labeled N/C (no-connect) are truly no-connect, and can be tied or left floating.
Figure 10-2. Device, ULPI Output Clock Mode Application Diagram
54 Application Information Copyright © 2009–2012, Texas Instruments Incorporated
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