Datasheet

TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012 www.ti.com
BITS FIELD NAME DESCRIPTION TYPE RESET
7 Reserved R 0
6 MNTR_VUSBIN_OK_LATCH Set to 1 when an unmasked event occurs on MNTR_VUSBIN_OK_LATCH. R 0
Clear on read register.
5 ABNORMALSTRESS_LATCH Set to 1 when an unmasked event occurs on ABNORMALSTRESS. Clear on R 0
read register.
4 ID_FLOAT_LATCH Set to 1 when an unmasked event occurs on ID_FLOAT. Clear on read R 0
register.
3 ID_RESC_LATCH Set to 1 when an unmasked event occurs on ID_RESC. Clear on read R 0
register.
2 ID_RESB_LATCH Set to 1 when an unmasked event occurs on ID_RESB. Clear on read R 0
register.
1 ID_RESA_LATCH Set to 1 when an unmasked event occurs on ID_RESA. Clear on read R 0
register.
0 BVALID_LATCH Set to 1 when an unmasked event occurs on VB_SESS_VLD. Clear on read R 0
register.
9.1.34 VENDOR_SPECIFIC3
ADDRESS OFFSET 0x85
PHYSICAL ADDRESS 0x85 INSTANCE USB_SCUSB
DESCRIPTION
TYPE RW
WRITE LATENCY
7 6 5 4 3 2 1 0
SOF_EN
CPEN_OD
RESERVED
IDGND_DRV
CPEN_ODOS
VUSB3V3_VSEL
BITS FIELD NAME DESCRIPTION TYPE RESET
7 Reserved RW 0
6 SOF_EN 0: HS USB SOF detector disabled. RW 0
1: Enable HS USB SOF detection when PHY is set in device mode.
SOF are output on CPEN pin. HS USB SOF (start-of-frame) output
clock is available on CPEN pin when this bit is set. HS USB SOF
packet rate is 8 kHz.
This bit is provided for debugging purpose only. It must never been
write to ‘1’ in functional mode
5 CPEN_OD This bit has no effect when CPEN_ODOS = ‘0’, else : RW 0
0: CPEN pad is in OS (Open Source) mode.
In this case CPEN pin has an internal NMOS driver, and will be active
LOW.
Externally there should be a pullup resistor on CPEN (min 1kohm) to a
supply voltage (max 3.6V).
1: CPEN pad is in OD (Open Drain) mode
In this case CPEN pin has an internal PMOS driver, and will be active
HIGH.
Externally there should be a pull-down resistor on CPEN (min 1 kΩ to
GND.
50 Register Map Copyright © 2009–2012, Texas Instruments Incorporated
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