Datasheet
TUSB1210
www.ti.com
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
9.1.26 VENDOR_SPECIFIC1
ADDRESS OFFSET 0x3D
PHYSICAL ADDRESS 0x3D INSTANCE USB_SCUSB
DESCRIPTION Power Control register .
TYPE RW
WRITE LATENCY
7 6 5 4 3 2 1 0
SPARE
SPARE
ID_RES_EN
BVALID_RISE
BVALID_FALL
ID_FLOAT_EN
MNTR_VUSBIN_OK_EN
ABNORMALSTRESS_EN
BITS FIELD NAME DESCRIPTION TYPE RESET
7 SPARE Reserved. The link must never write a 1b to this bit. RW 0
6 MNTR_VUSBIN_OK_EN When set to 1, it enables RX CMDs for high to low or low to high RW 0
transitions on MNTR_VUSBIN_OK. This bit is provided for debugging
purposes.
5 ID_FLOAT_EN When set to 1, it enables RX CMDs for high to low or low to high RW 0
transitions on ID_FLOAT. This bit is provided for debugging purposes.
4 ID_RES_EN When set to 1, it enables RX CMDs for high to low or low to high RW 0
transitions on ID_RESA, ID_RESB and ID_RESC. This bit is provided for
debugging purposes.
3 BVALID_FALL Enables RX CMDs for high to low transitions on BVALID. When BVALID RW 0
changes from high to low, the USB TRANS will send an RX CMD to the
link with the alt_int bit set to 1b.
This bit is optional and is not necessary for OTG devices. This bit is
provided for debugging purposes. Disabled by default.
2 BVALID_RISE Enables RX CMDs for low to high transitions on BVALID. When BVALID RW 0
changes from low to high, the USB Trans will send an RX CMD to the link
with the alt_int bit set to 1b.
This bit is optional and is not necessary for OTG devices. This bit is
provided for debugging purposes. Disabled by default.
1 SPARE Reserved. The link must never write a 1b to this bit. RW 0
0 ABNORMALSTRESS_E When set to 1, it enables RX CMDs for low to high and high to low RW 0
N transitions on ABNORMALSTRESS. This bit is provided for debugging
purposes.
9.1.27 VENDOR_SPECIFIC1_SET
ADDRESS OFFSET 0x3E
PHYSICAL ADDRESS 0x3E INSTANCE USB_SCUSB
DESCRIPTION This register doesn't physically exist.
It is the same as the func_ctrl register with read/set-only property (write '1' to
set a particular bit, a write '0' has no-action).
TYPE RW
WRITE LATEN CY
Copyright © 2009–2012, Texas Instruments Incorporated Register Map 45
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