Datasheet

TUSB1210
www.ti.com SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
BITS FIELD NAME DESCRIPTION TYPE RESET
3 SESSEND_LATCH Set to 1 by the PHY when an unmasked event occurs on SessEnd. R 0
Cleared when this register is read.
2 SESSVALID_LATCH Set to 1 by the PHY when an unmasked event occurs on SessValid. R 0
Cleared when this register is read. SessValid is the same as UTMI+
AValid.
1 VBUSVALID_LATCH Set to 1 by the PHY when an unmasked event occurs on VbusValid. R 0
Cleared when this register is read.
0 HOSTDISCONNECT_LAT Set to 1 by the PHY when an unmasked event occurs on R 0
CH Hostdisconnect. Cleared when this register is read. Applicable only in
host mode.
NOTE: As this IT is enabled by default, the reset value depends on the
host status
Reset value is '0' when host is connected.
Reset value is '1' when host is disconnected.
9.1.22 DEBUG
ADDRESS OFFSET 0x15
PHYSICAL ADDRESS 0x15 INSTANCE USB_SCUSB
DESCRIPTION Indicates the current value of various signals useful for debugging.
TYPE R
WRITE LATENCY
7 6 5 4 3 2 1 0
Reserved Reserved Reserved Reserved Reserved Reserved
LINESTATE
BITS FIELD NAME DESCRIPTION TYPE RESET
7 Reserved R 0
6 Reserved R 0
5 Reserved R 0
4 Reserved R 0
3 Reserved R 0
2 Reserved R 0
1:00 LINESTATE These signals reflect the current state of the single ended receivers. They directly R 0x0
reflect the current state of the DP (LineState[0]) and DM (LineState[1]) signals.
Read 0x0: SE0 (LS/FS), Squelch (HS/Chirp)
Read 0x1: LS: 'K' State,
FS: 'J' State,
HS: !Squelch,
Chirp: !Squelch & HS_Differential_Receiver_Output
Read 0x2: LS: 'J' State,
FS: 'K' State,
HS: Invalid,
Chirp: !Squelch & !HS_Differential_Receiver_Output
Read 0x3: SE1 (LS/FS), Invalid (HS/Chirp)
9.1.23 SCRATCH_REG
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