Datasheet
TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012
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BITS FIELD NAME DESCRIPTION TYPE RESET
7 Reserved R 0
6 SUSPENDM RW 1
5 RESET RW 0
4:03 OPMODE RW 0x0
2 TERMSELECT RW 0
1:00 XCVRSELECT RW 0x1
9.1.8 IFC_CTRL
ADDRESS OFFSET 0x07
PHYSICAL ADDRESS 0x07 INSTANCE USB_SCUSB
DESCRIPTION Enables alternative interfaces and PHY features.
TYPE RW
WRITE LATENCY
7 6 5 4 3 2 1 0
CARKITMODE
AUTORESUME
CLOCKSUSPENDM
INDICATORPASSTHRU
FSLSSERIALMODE_6PIN
FSLSSERIALMODE_3PIN
INDICATORCOMPLEMENT
INTERFACE_PROTECT_DISABLE
BITS FIELD NAME DESCRIPTION TYPE RESET
7 INTERFACE_PROTECT Controls circuitry built into the PHY for protecting the ULPI interface when the RW 0
_DISABLE link tri-states stp and data.
0b: Enables the interface protect circuit
1b: Disables the interface protect circuit
6 INDICATORPASSTHRU Controls whether the complement output is qualified with the internal RW 0
vbusvalid comparator before being used in the VBUS State in the RXCMD.
0b: Complement output signal is qualified with the internal VBUSVALID
comparator.
1b: Complement output signal is not qualified with the internal VBUSVALID
comparator.
5 INDICATORCOMPLEM Tells the PHY to invert EXTERNALVBUSINDICATOR input signal, generating RW 0
ENT the complement output.
0b: PHY will not invert signal EXTERNALVBUSINDICATOR (default)
1b: PHY will invert signal EXTERNALVBUSINDICATOR
4 AUTORESUME Enables the PHY to automatically transmit resume signaling. RW 1
Refer to USB specification 7.1.7.7 and 7.9 for more details.
0 = AutoResume disabled
1 = AutoResume enabled (default)
3 CLOCKSUSPENDM Active low clock suspend. Valid only in Serial Modes. Powers down the RW 0
internal clock circuitry only. Valid only when SuspendM = 1b. The PHY must
ignore ClockSuspend when SuspendM = 0b. By default, the clock will not be
powered in Serial and Carkit Modes.
0b : Clock will not be powered in Serial and UART Modes.
1b : Clock will be powered in Serial and UART Modes.
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