Datasheet

TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012 www.ti.com
5.3.2 Timers and Debounce
PARAMETER COMMENTS MIN TYP MAX UNIT
T
DEL_CS_SUPPLYOK
Chip-select-to-supplies OK delay 2.84 4.10 ms
T
DEL_RST_DIR
RESETB to PHY PLL locked and DIR 0.54 0.647 ms
falling-edge delay
T
VBBDET
V
BAT
detection delay 10 us
T
BGAP
Bandgap power-on delay 2 ms
T
PWONVDD15
V
DD15
power-on delay 100 us
T
PWONCK32K
32-KHz RC-OSC power-on delay 125 us
T
DELRSTPWR
Power control reset delay 61 us
T
DELMNTRVIOEN
Monitor enable delay 91.5 us
T
MNTR
Supply monitoring debounce 183.1 us
T
DELVDD33EN
V
DD33
LDO enable delay 93.75 us
T
DELRESETB
RESETB internal delay 244.1 us
T
PLL
PLL lock time 300 us
16 Power Module Copyright © 2009–2012, Texas Instruments Incorporated
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