Datasheet

TUSB1210
SLLSE09F –NOVEMBER 2009–REVISED AUGUST 2012 www.ti.com
4.4 Clock 32 kHz
An internal clock generator running at 32 kHz has been implemented to provide a low-speed, low-power
clock to the system
Table 4-3. Performances
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output duty cycle Input duty cycle 40–60% 48 50 52 %
Output frequency 23 32 38 kHz
4.5 Reset
All logic is reset if CS = 0 or V
BAT
are not present.
All logic (except 32 kHz logic) is reset if V
DDIO
is not present.
PHY logic is reset when any supplies are not present (V
DDIO
, V
DD15
, V
DD18
, V
DD33
) or if RESETB pin is low.
TUSB1210 may be reset manually by toggling the RESETB pin to GND for at lease 200 ns.
If manual reset via RESETB is not required then RESETB pin may be tied to V
DDIO
permanently.
12 Clock System Copyright © 2009–2012, Texas Instruments Incorporated
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