Marine Radio - Marine Radio Decoder User Manual

13.1.2 Unexpected Frame Length: F
13.1.3 Unexpected Prolog Length: P
13.1.4 Unexpected Subframe Length: SF
13.1.5 Unexpected Reliability Length: R
13.1.6 Unexpected Signal to Noise Ratio: SNR
13.1.7 Unexpected Interleaver Table Load: INT
13.1.8 Unexpected Output Parameters Load: OP
13.1.9 Unexpected Memory Access: ACC
Errors and Status www.ti.com
The F bit is set to 1 if the programmed frame length is strictly smaller than 40 or is strictly greater than
20730 for standalone mode.
The F bit is set to 1 if the programmed frame length has the following values for shared processing mode:
1. Frame length < 256 or frame length > 20480 or (frame length)%256 != 0 if opmode = 1 or 2.
2. Frame length < 128 or frame length > 20480 if opmode = 3.
The P bit is set to 1 if the specified prolog length is strictly greater than 48. Values smaller than 4 are
ignored by the hardware and 24 is used.
The SF bit is set to 1 if the specified subframe length is strictly greater than 20480 in shared processing
mode.
The R bit is set to 1 if the specified reliability length minus 1 is strictly smaller than 40 or greater than 128
in SA mode.
The R bit is set to 1 if the specified reliability length is not equal to 128 in SP mode if opmode = 1 or 2.
The R bit is set to 1 if the specified reliability length is less than 65 in SP mode if opmode = 3.
The SNR bit is set to 1 if the signal to noise ratio threshold is greater than 100.
The INT bit is set to 1 if loading an interleaver table has been requested in SP mode.
The OP bit is set to 1 if loading the output parameters has been requested in SP mode.
The ACC bit is set to 1 when an unexpected memory access occurs. This can be used to spot any
EDMA3 programming issues. This can occur when:
• TCP2 is waiting for input configuration parameters state and memory access to any TCP2 memory but
the interleaver memory is performed
• TCP2 is waiting for systematics and parities state and memory access to any TCP2 memory other than
the TCPINTER memory
• TCP2 is waiting for a prioris state and memory access to any TCP2 memory other than the TCPAP
memory
• TCP2 is waiting for extrinsics state and memory access to any TCP2 memory other than the TCPEXT
memory
• TCP2 is waiting for hard decisions state and memory access to any TCP2 memory other than the
TCPHD memory
• TCP2 is waiting for output parameters state and memory access to any TCP2 memory
TMS320C6457 Turbo-Decoder Coprocessor 276 SPRUGK1 – March 2009
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