Marine Radio - Marine Radio Decoder User Manual

Input config
params
Syst&Par
SF1 SF1
Extrinsics
TCP processing
TCPXEVT TCPXEVT TCPREVT TCPXEVT
MAP1
TCP processing
TCPXEVT
Input config
params
TCPXEVT TCPREVT
SF2
Syst&Par Extrinsics
SF2
TCPXEVT
2 subframes
TCPXEVT
Input config
params
TCPXEVT
SF1
Syst&Par Apriori
SF1
TCPXEVT TCPREVT
Extrinsics
SF1
TCPXEVT TCPXEVT
Input config
params
TCPXEVT
ExtrinsicsSyst&Par
SF2
Apriori
SF2
TCPXEVT TCPREVT
SF2
TCPXEVT
MAP 1.2
2 subframes
TCP processing
TCP processing
12 Debug Mode: Pause After Each Map
13 Errors and Status
13.1 Errors
13.1.1 Error Status: ERR
www.ti.com Debug Mode: Pause After Each Map
Figure 101. TCP2 Events Generation in Shared-Processing (SP) Mode
The TCPEXE register starts, resets, and places TCP2 into debug mode. Writing the following to TCPEXE
will place TCP2 into the defined modes.
• 0 = no instruction. Value at reset or value written by the coprocessor when previous instruction is read
and its execution is ongoing. DSP may test the status word in the output control memory to check if the
instruction is being executed.
• 1 = start. The C6457 CPU requests the coprocessor to start a processing block. The first action of the
coprocessor is to stop any of the ongoing processing, reset all its pointers and start a new process by
generating the first XEVT to trigger EDMA3 transfer of the input control words.
• 4 = debug mode. Normal initialization and wait in MAP state 0.
• 5 = debug mode. Execute one MAP decode and wait in MAP state 6.
• 6 = debug mode. Execute remaining MAP decodes and complete normal ending.
• 7 = SOFT RESET. Soft reset all TCP2 registers, except for endianness, execution, emulation register,
and all other internal registers.
The TCP2 error register (TCPERR) flags any errors that occurred in the TCP2. Once the errors are
flagged, the TCP2 stops, and a TCP2_INT interrupt is generated. TCP2_INT has an interrupt selector
value of 31. For details on how to set up interrupts, see the TMS320C64x+ Megamodule Reference Guide
(SPRU871 ).
Reading TCPERR resets both TCPERR and the TCP2 status register (TCPSTAT) to their default values;
that is, the TCP2 waits for a new START command.
The ERR bit is set to 1 in case of error.
SPRUGK1 – March 2009 TMS320C6457 Turbo-Decoder Coprocessor 2 75
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