Marine Radio - Marine Radio Decoder User Manual

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53 TCP2 Endian Register (TCPEND) ....................................................................................... 44
54 TCP2 Error Register (TCPERR).......................................................................................... 45
55 TCP2 Status Register (TCPSTAT) ....................................................................................... 47
56 TCP2 Emulation Register (TCPEMU) ................................................................................... 49
57 Data Source - EDMA3 (Big Endian) ..................................................................................... 50
58 Data Destination - Kernel (Little Endian) ................................................................................ 50
59 Data Source - Kernel (Little Endian) ..................................................................................... 50
60 Data Destination - EDMA3 (Big Endian) ................................................................................ 50
61 Data Memory................................................................................................................ 51
62 EN = 1 (Little-Endian Mode) Rate = 1/2 ................................................................................. 51
63 EN = 0 (Big-Endian Mode) Rate = 1/2................................................................................... 51
64 EN = 1 (Little-Endian Mode) Rate = 1/3 ................................................................................. 51
65 EN = 0 (Big-Endian Mode) Rate = 1/3................................................................................... 51
66 EN = 1 (Little-Endian Mode) Rate = 1/4 ................................................................................. 51
67 EN = 0 (Big-Endian Mode) Rate = 1/4................................................................................... 52
68 EN = 1 (Little-Endian Mode) Rate = 1/5 ................................................................................. 52
69 EN = 0 (Big-Endian Mode) Rate = 1/5................................................................................... 52
70 EN = 1 (Little-Endian Mode) Rate = 3/4 ................................................................................. 52
71 EN = 0 (Big-Endian Mode) Rate = 3/4................................................................................... 53
72 Source of Endianness Manager - Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER = 0) ............ 53
73 Destination of Endianness Manager - Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER = 0) ....... 53
74 Source of Endianness Manager - Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER = 1) ............ 53
75 Destination of Endianness Manager - Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER = 1) ....... 53
76 Source of Endianness Manager - Trellis Stage Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER
= 0) ........................................................................................................................... 53
77 Destination of Endianness Manager (OUT_ORDER = 0) ............................................................. 54
78 Trellis Stage Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER = 1) ..................................... 54
79 Trellis Stage Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER = 1) ..................................... 54
80 Data Source = Kernel ...................................................................................................... 54
81 Data Destination = EDMA3 EN = 0 (Big-Endian Mode) ............................................................... 54
82 TCP_ENDIAN Register .................................................................................................... 55
83 Interleaver Indexes in DSP Memory (ENDIAN_INTR = 1) ............................................................ 56
84 Data Source - EDMA3 (ENDIAN_INTR = 1) ............................................................................ 56
85 Data Destination - Kernel (ENDIAN_INTR = 1) ........................................................................ 56
86 Interleaver Indexes in DSP Memory (ENDIAN_INTR = 0) ............................................................ 56
87 Data Source - EDMA3 (ENDIAN_INTR = 0) ............................................................................ 57
88 Data Destination - Kernel (ENDIAN_INTR = 0) ........................................................................ 57
89 Extrinsic in DSP Memory (ENDIAN_EXTR = 1) ........................................................................ 57
90 Data Source - Kernel (ENDIAN_EXTR = 1) ............................................................................ 58
91 Data Destination - EDMA3 (ENDIAN_EXTR = 1) ...................................................................... 58
92 Extrinsic in DSP Memory (ENDIAN_EXTR = 0) ........................................................................ 59
93 Data Source - Kernel (ENDIAN_EXTR = 0) ............................................................................ 59
94 Data Destination - EDMA3 (ENDIAN_EXTR = 0) ...................................................................... 59
95 MAP Unit Block Diagram .................................................................................................. 60
96 Sliding Windows and Sub-blocks Segmentation (Example with 5 Sub-blocks, frame length ≤ 20730) ......... 61
97 Shared Processing Subframe Segmentation (Example with 5 Subframes) ........................................ 62
98 Example R Formula ........................................................................................................ 63
99 EDMA3 Parameters Structure ............................................................................................ 65
100 TCP2 Events Generation in Standalone (SA) Mode................................................................... 74
101 TCP2 Events Generation in Shared-Processing (SP) Mode ......................................................... 75
6 List of Figures SPRUGK1 – March 2009
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