Marine Radio - Marine Radio Decoder User Manual

7.1.4 Extrinsic Data
7.1.4.1 ENDIAN_EXTR = 1
XT0
XT1
XT2
XT3
XT4
XT6
XT7
XT5
Base 0
Base 7
Endian_Extr=1
XT7 XT6 XT5 XT4 XT0 XT2 XT3 XT1
Endianness
manager
XT7 XT6 XT5 XT4 XT3 XT2 XT1 XT0
63 0 63 0
EDMA3
TCP
Kernel
Memory
www.ti.com Endianness
Figure 87. Data Source - EDMA3 (ENDIAN_INTR = 0)
63 48 47 32 31 16 15 1
INTER1 INTER0 INTER3 INTER2
Figure 88. Data Destination - Kernel (ENDIAN_INTR = 0)
63 48 47 32 31 16 15 1
INTER3 INTER2 INTER1 INTER0
Table 37. Extrinsic Data
Little_big_endian ENDIAN_INTR Description (MSB to LSB)
0 0 3,2,1,0,7,6,5,4 ⇒ 7,6,5,4,3,2,1,0 (bytes)
0 1 0,1,2,3,4,5,6,7 ⇒ 7,6,5,4,3,2,1,0 (bytes)
1 0 Endianness manager has no effect
7,6,5,4,3,2,1,0 ⇒ 7,6,5,4,3,2,1,0 (bytes)
1 1 Endianness manager has no effect
7,6,5,4,3,2,1,0 ⇒ 7,6,5,4,3,2,1,0 (bytes)
If ENDIAN_EXTR = 1, data are saved in their native format (8 bits) in the DSP (see Table 38 ).
Table 38. Extrinsic in DSP Memory (ENDIAN_EXTR =
1)
Address (hex bytes) Data
Base EXT0
Base + 1 EXT1
Base + 2 EXT2
Base + 3 EXT3
Base + 4 EXT4
Base + 5 EXT5
Base + 6 EXT6
Base + 7 EXT7
Figure 89. Extrinsic in DSP Memory (ENDIAN_EXTR = 1)
They have to be swapped as described in Figure 90 and Figure 91 .
SPRUGK1 – March 2009 TMS320C6457 Turbo-Decoder Coprocessor 2 57
Submit Documentation Feedback