Marine Radio - Marine Radio Decoder User Manual

7.1.2 TCP_ENDIAN Register for Endianness Manager
Endianness www.ti.com
Figure 77. Destination of Endianness Manager (OUT_ORDER = 0)
63 62 32 31 1 0
Stage Stage Stage Stage Stage Stage
N - 32 N - 33 N - 63 N N - 30 N - 31
4. OUT_ORDER = 1 EN = 1 (Little-Endian Mode)
Figure 78. Trellis Stage Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER = 1)
63 62 32 31 1 0
Stage Stage Stage Stage Stage Stage
N N - 1 N - 31 N - 32 N - 62 N - 63
Figure 79. Trellis Stage Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER = 1)
63 62 32 31 1 0
Stage Stage Stage Stage Stage Stage
N - 63 N - 62 N - 32 N - 31 N - 1 N
Hard decisions are packed in a 32 bit word inside the TCP2. Data will be saved in word format (32 bits) in
the DSP.
Table 32. Hard Decisions in DSP Memory
Address (hex bytes) Data
Base HD0 (32 hard decisions)
Base + 4 HD1 (32 hard decisions)
They have to be swapped as described in Figure 80 and Figure 81 .
Figure 80. Data Source = Kernel
15 8 7 0
HD1 HD0
R/W R/W
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Figure 81. Data Destination = EDMA3 EN = 0 (Big-Endian Mode)
15 8 7 0
HD0 HD1
R/W R/W
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
TCP2 input/output data are of different widths and storage in the DSP memory subsystem will be different
whether they are saved in native or word format. However, EDMA3 will always read and write words.
There is a need to define a way of handling the data depending on whether they are saved in native or
words format. Table 33 summarizes the different data formats, as well as the memory-mapped register
TCP_ENDIAN programming (see Figure 82 ).
54 TMS320C6457 Turbo-Decoder Coprocessor 2 SPRUGK1 – March 2009
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