Datasheet

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TIMING DIAGRAM
t
td
t
a
t
sck
t
Lead
t
Lag
t
wsck
t
wsck
t
r
t
f
t
v
t
ho
t
dis
t
hi
t
su
MSB OUT BIT . . . 1 LSB OUT
MSB IN BIT . . . 1 LSB IN
SS
SCLK
MISO
MOSI
TIMING CHARACTERISTICS
(1) (2)
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
PIN DESCRIPTION (continued)
VFBGA TQFP I/O NAME DESCRIPTION
BALL PIN
D10 61 I Y+ Y+ position input
C11 62 I HPVDD Analog supply for headphone amplifier and touch screen circuitry
B11 63 I AUX1 SAR auxiliary analog input 1
B10 64 I AUX2 SAR auxiliary analog input 2
All specifications typical at -40 °C to +85 °C, +V
DD
= +2.7 V, POL = 1
Parameter Symbol Min Max Units
SCLK period t
sck
30 ns
Enable lead time t
Lead
15 ns
Enable lag time t
Lag
15 ns
Sequential transfer delay t
td
30 ns
Data setup time t
su
10 ns
Data hold time (inputs) t
hi
10 ns
Data hold time (outputs) t
ho
0 ns
Slave access time t
a
15 ns
Slave DOUT disable time t
dis
15 ns
Data valid t
v
10 ns
Rise time t
r
30 ns
Fall time t
f
30 ns
(1) All input signals are specified with t
R
= t
F
= 5ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2) See timing diagram, above.
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