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Bit 13 — PLLO

TSC2301

SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004

Bit 15 — SDAV (write only)

SPI Data Available. This read-only bit mirrors the function of the DAV pin. This bit is provided so that the host

processor can poll the SPI interface to see whether data is available, without dedicating a GPIO pin from the host

processor to the TSC2301 DAV pin. This bit is normally high, goes low when touch screen or keypad data is

available, and is reset high when all the new data has been read. When written to, this bit becomes KBC1,

operation detailed below.

Table 24. SPI Data Available (Read Only)

SDAV Description

0 Touchscreen data is available.

1 No new data available (default)

Bits [15:14] — KBC1-KBC0 (write mode)

KBIRQ Control (write-only mode). These bits control the behavior of the KBIRQ signal. There are four possible

ways to de-assert the KBIRQ signal once it goes low. These bits control which particular events cause the

KBIRQ signal to be de-asserted (go high). The four de-assertion possibilities are:

A. Hardware or software reset. Hardware reset—RESET pin asserted (high) and subsequently de-asserted.

Software reset—writing BB00h to register 04h, page 1.

B. Writing 1 to the SCS bit. Bit 14 of register 01h, page 1

C. Releasing the pressed key on the keypad.

D. Reading the keypad data register (register 04h, page0).

Refer to the table below to see which settings of the KBC1 - KBC0 correspond to the KBIRQ reset events. When

read, KBC1 becomes SDAV operation detailed above. KBC0 operates the same as in read and write modes.

Table 25. KBIRQ Behavior Possibilities

KBC1 KBC0 KBIRQ Reset Event

0 0 De-assertion possibility A or B or C.

0 1 De-assertion possibility A or B.

1 0 De-assertion possibility A or B or C or D.

1 1 De-assertion possibility A or B or D (default).

PLL Output on GPIO_0. This bit allows the user to receive the output of the audio codec internal PLL. This bit is

provided so the host processor can use the output of the PLL, to generate its I

S signals in sync with an external

MCLK or crystal oscillator. Writing a 0 to this bit connects the output of the PLL to the GPIO_0 pin. Otherwise,

the GPIO_0 pin operates as normal.

Table 26. PLL Output

PLLO Description

0 Output PLL on GPIO_0.

1 GPIO_0 operates as normal (default).