Datasheet

2
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TSC2200
SBAS191F
ABSOLUTE MAXIMUM RATINGS
(1)
V
DD
to GND ........................................................................ –0.3V to +6.0V
V
BAT
Input Voltage to GND ............................................... –0.3V to +6.0V
Analog Input Voltage to GND (except V
BAT
) ........... –0.3V to V
DD
+ 0.3V
Digital Input Voltage to GND ................................... –0.3V to V
DD
+ 0.3V
Operating Temperature Range ...................................... –40°C to +105°C
Storage Temperature Range .........................................–65°C to +150°C
Junction Temperature (T
J
Max) .................................................... +150°C
TSSOP Package
Power Dissipation .................................................... (T
J
Max – T
A
)/ θ
JA
θ
JA
Thermal Impedance .......................................................... 90°C/W
Lead Temperature, Soldering
Vapor Phase (60s) ............................................................ +215°C
Infrared (15s) ..................................................................... +220°C
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
INTEGRAL SPECIFIED
LINEARITY PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT ERROR (LSB) PACKAGE-LEAD
DESIGNATOR
(1)
RANGE MARKING NUMBER MEDIA, QUANTITY
TSC2200 ±2 TSSOP-28 PW –40°C to +85°C TSC2200I TSC2200IPW Rails, 50
"" " " " "TSC2200IPWR Tape and Reel, 2000
TSC2200 ±2 QFN-32 RHB –40°C to +85°C TSC2200I TSC2200IRHB Tubes, 72
"" " " " "TSC2200IRHBR Tape and Reel, 2500
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper han-
dling and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
TIMING DIAGRAM
All specifications typical at –40°C to +85°C, +V
DD
= +2.7V.
t
td
t
Lag
t
dis
t
Lead
t
sck
t
wsck
t
wsck
t
hi
t
su
t
ho
t
a
t
v
t
r
t
f
SS
SCLK
MSB OUT
MSB IN LSB IN
LSB OUTBIT 6 ... 1
BIT 6 ... 1
MISO
MOSI
PARAMETER CONDITIONS MIN TYP MAX UNITS
SCLK Period t
sck
30 ns
Enable Lead Time t
Lead
15 ns
Enable Lag Time t
Lag
15 ns
Sequential Transfer Delay t
td
30 ns
Data Setup Time t
su
10 ns
Data Hold Time (inputs) t
hi
10 ns
Data Hold Time (outputs) t
ho
0ns
Slave Access Time t
a
15 ns
Slave D
OUT
Disable Time t
dis
15 ns
Data Valid t
v
10 ns
Rise Time t
r
30 ns
Fall Time t
f
30 ns
TIMING CHARACTERISTICS
(1)(2)
At –40°C to +85°C, +V
DD
= +2.7V, V
REF
= +2.5V, unless otherwise noted.
TSC2200
NOTES: (1) All input signals are specified with t
r
= t
f
= 5ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2. (2) See timing diagram below.