Datasheet

13
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TSC2200
SBAS191F
ADDR REGISTER
00 X
01 Y
02 Z
1
03 Z
2
04 KPDATA
05 BAT1
06 BAT2
07 AUX1
08 AUX2
09 TEMP1
0A TEMP2
0B DAC
0C Reserved
0D Reserved
0E Reserved
0F Reserved
10 ZERO
11 Reserved
12 Reserved
13 Reserved
14 Reserved
15 Reserved
16 Reserved
17 Reserved
18 Reserved
19 Reserved
1A Reserved
1B Reserved
1C Reserved
1D Reserved
1E Reserved
1F Reserved
PAGE 0: DATA REGISTERS PAGE 1: CONTROL REGISTERS
ADDR REGISTER
00 ADC
01 KEY
02 DACCTL
03 REF
04 RESET
05 CONFIG
06 Reserved
07 Reserved
08 Reserved
09 Reserved
0A Reserved
0B Reserved
0C Reserved
0D Reserved
0E Reserved
0F Reserved
10 KPMASK
11 Reserved
12 Reserved
13 Reserved
14 Reserved
15 Reserved
16 Reserved
17 Reserved
18 Reserved
19 Reserved
1A Reserved
1B Reserved
1C Reserved
1D Reserved
1E Reserved
1F Reserved
TABLE III. TSC2200 Memory Map.
FIGURE 7. Write and Read Operation of TSC2200 Interface.
Write Operation
Read Operation
Command Word Command Word
Data
Data Data
SS
SCLK
MOSI
MISO
To read all the first page of memory, for example, the host
processor must send the TSC2200 the command 8000
H
—this
specifies a read operation beginning at Page 0, Address 0. The
processor can then start clocking data out of the TSC2200. The
TSC2200 will automatically increment its address pointer to the
end of the page; if the host processor continues clocking data
out past the end of a page, the TSC2200 will simply send back
the value FFFF
H
.
Likewise, writing to Page 1 of memory would consist of the
processor writing the command 0800
H
, which would specify a
write operation, with PG0 set to 1, and all the ADDR bits set
to 0. This would result in the address pointer pointing at the
first location in memory on Page 1. See the TSC2200 Memory
Map section for details of register locations. Figure 7 shows an
example of a complete data transaction between the host
processor and the TSC2200.
TSC2200 MEMORY MAP
The TSC2200 has several 16-bit registers that allow control of
the device as well as provide a location for results from the
TSC2200 to be stored until read by the host microprocessor.
These registers are separated into two pages of memory in the
TSC2200: a Data page (Page 0) and a Control page (Page 1).
The memory map is shown in Table III.