Datasheet

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Program Description
3.4.2 PLL Section
There is an on-chip phase-locked loop (PLL) in the TSC2111. The PLL can be enabled or disabled, based
on the given master clock (MCLK) to the TSC2111 and the required reference frequency (FSref) for the
codec. For more details on the PLL, refer to the TSC2111 data sheet.
The PLL can be set on the PLL Secton of Audio 1 screen (Figure 10 ).
The default frequencies for this EVM board are
• MCLK = 11.2896 MHz
• Reference sample rate = 44.1 kHz
At the bottom of the section, the corresponding FSref frequency is shown based on the selection of:
1. the Q-value if the PLL has not been enabled, or
2. the P, J, D values if the PLL has been enabled.
3.4.3 ADC Section
This section (Audio 1 Tab, Figure 10 ) configures the audio ADC power and the analog input source.
By default, the audio ADC is powered up so that the audio-recording function can start running with the
default settings. Checking Power Down ADC disables the audio ADC.
The ADC sample rate can be set as a divider frequency from the reference frequency, FSref. For
example, when FSref = 44.1 kHz (set in the INTERFACE section of the same tab), an 8-K sample rate is
obtained by setting the divider to 5.5 (44100/5.5 = 8018 Hz).
The audio ADC also has a high-pass filter, which is a sub-multiple of the sample rate, to remove dc or low
frequency components from the input signal.
The input signal to the audio ADC can be selected from different analog resources under different modes
using the Select ADC Input Source option list. The microphone input from the headset or the handset can
be selected; the single-ended or the differential input (paired with AUX1 or AUX2) can be used.
The cell-phone input can also be connected to the audio ADC.
3.4.4 DAC/Outputs Section
This section configures the audio DAC power and all functions of the analog outputs, such as power, gain,
mode, and destination, which identifies the analog output pin or pins where the analog output signal is
sent.
In the Power Down subsection, the DAC and the output driver circuits can be powered up/down
individually. By checking a checkbox, the corresponding TSC2111 circuit is powered down.
In the SC Protect subsection, the short-circuit (SC) protection function can be enabled or disabled. When
the short-circuit protection function is enabled and a short-circuit occurs, all analog outputs are disabled
and the corresponding flag is set. For example, to set the headset SC protection, check the box. In the
event of a headset short circuit, all analog outputs are disabled, and D1 of control registers in page 2
address 0x1D is set. The TSC2111 requires hardware or software reset to return to normal operation.
Similar to the ADC, the DAC sample rate can be set as a divider frequency from the reference FSref
frequency, through the DAC Sample Rate option list.
The TSC2111 has the capability to route the stereo DAC output signals to the selected analog output. To
route the signals to the headset drivers (SP1 and SP2 pins), select from the DAC Output to lists. By
default, the left channel DAC output is routed to SP1 and the right channel to SP2.
The signal routed to SP1 can also be output to the loud speaker (OUT8P/OUT8N), if the SP1 to Loud SP
checkbox is checked.
The SP1 output can be used in single-ended or differential mode. In single-ended mode, it is driven as
one channel of the stereo headset outputs, and the audio sound is output through a headset at J11 on the
TSC2111EVM daughtercard. In differential mode, the SP1 is paired with the OUT32N pin as the receiver
driver, and the audio sound is output through a speaker connected to the terminal block J2 on the
TSC2111EVM. By default, the SP1 is set to single-ended mode.
SLAU178 – April 2006 TSC2111EVM and TSC2111EVM-PDK 19
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