Datasheet
TSC2101
SLAS392D− JUNE 2003 − REVISED MAY 2005
www.ti.com
50
BIT FUNCTION
READ/
WRITE
RESET
VALUE
NAME
D10 XSTAT 0 R X Data Register Status
0 => No new data is available in X−data register
1 => New data for X−coordinate is available in register
Note: This bit gets cleared only after the converted data of X coordinate has been completely read
out of the register. This bit is not valid in case of buffer mode.
D9 YSTAT 0 R Y Data Register Status
0 => No new data is available in Y−data register
1 => New data for Y−coordinate is available in register
Note: This bit gets cleared only after the converted data of Y coordinate has been completely read
out of the register. This bit is not valid in case of buffer mode.
D8 Z1STAT 0 R Z1 Data Register Status
0 => No new data is available in Z1−data register
1 => New data is available in Z1−data register
Note: This bit gets cleared only after the converted data of Z1 coordinate has been completely read
out of the register. This bit is not valid in case of buffer mode.
D7 Z2STAT 0 R Z2 Data Register Status
0 => No new data is available in Z2−data register
1 => New data is available in Z2−data register
Note: This bit gets cleared only after the converted data of Z2 coordinate has been completely read
out of the register. This bit is not valid in case of buffer mode.
D6 BSTAT 0 R BAT Data Register Status
0 => No new data is available in BAT data register
1 => New data is available in BAT data register
Note: This bit gets cleared only after the converted data of BAT has been completely read out of the
register. This bit is not valid in case of buffer mode.
D5 0 R Reserved
D4 AX1STAT 0 R AUX1 Data Register Status
0 => No new data is available in AUX1−data register
1 => New data is available in AUX1−data register
Note: This bit gets cleared only after the converted data of AUX1 has been completely read out of
the register. This bit is not valid in case of buffer mode.
D3 AX2STAT 0 R AUX2 Data Register Status
0 => No new data is available in AUX2−data register
1 => New data is available in AUX2−data register
Note: This bit gets cleared only after the converted data of AUX2 has been completely read out of
the register. This bit is not valid in case of buffer mode.
D2 T1STAT 0 R TEMP1 Data Register Status
0 => No new data is available in TEMP1−data register
1 => New data is available in TEMP1−data register
Note: This bit gets cleared only after the converted data of TEMP1 has been completely read out of
the register. This bit is not valid in case of buffer mode.
D1 T2STAT 0 R TEMP2 Data Register Status
0 => No new data is available in TEMP2−data register
1 => New data is available in TEMP2−data register
Note: This bit gets cleared only after the converted data of TEMP2 has been completely read out of
the register. This bit is not valid in case of buffer mode.
D0 0 R Reserved