Datasheet

TSC2101
SLAS392D− JUNE 2003 − REVISED MAY 2005
www.ti.com
3
Terminal Functions
PIN NAME DESCRIPTION PIN NAME DESCRIPTION
1 IOVDD IO Supply 25 MIC_DETECT_IN Microphone detect input
2 PWR_DN Hardware power down 26 OUT32N Receiver driver output
3 RESET Hardware reset 27 SPK1 Headset driver output/receiver driver output
4 GPIO2 General purpose IO 28 SPK2 Headset driver output
5 GPIO1 General purpose IO 29 DRVDD Headphone driver power supply
6 AVDD2 Touch screen drivers, PLL analog
power supply
30 SPKFC Driver feedback/ speaker detect input
7 AVSS2 Analog ground 31 VGND Virtual ground for audio output
8 AVDD1 Audio ADC, DAC, reference, SAR
ADC analog power supply
32 DRVSS1 Driver ground
9 X+ X+ Position input and driver 33 OUT8N Loudspeaker driver output
10 Y+ Y+ Position input and driver 34 BVDD Battery power supply
11 X− X− Position input and driver 35 OUT8P Loudspeaker driver output
12 Y− Y− Position input and driver 36 DRVSS2 Driver ground
13 AVSS1 Analog ground 37 PINTDAV Pin interrupt/data available output
14 VREF Reference voltage 38 SS SPI Slave select input
15 VBAT Battery monitor input 39 MOSI SPI Serial data input
16 AUX2 Secondary auxiliary input 40 MISO SPI Serial data output
17 AUX1 First auxiliary input 41 SCLK SPI Serial clock input
18 BUZZ_IN Buzzer input 42 MCLK Master clock
19 CP_OUT Output to cell phone module 43 SDOUT Audio data output
20 CP_IN Input from cell phone module 44 SDIN Audio data input
21 MICIN_HND Handset microphone input 45 WCLK Audio word clock
22 MICBIAS_HND Handset microphone bias voltage 46 BCLK Audio bit clock
23 MICIN_HED Headset microphone input 47 DVDD Digital core supply
24 MICBIAS_HED Headset microphone bias voltage 48 DVSS Digital core and IO ground
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1), (2)
UNITS
AVDD1/2 to AVSS1/2 −0.3 V to 3.9 V
DRVDD to DRVSS1/2 −0.3 V to 3.9 V
BVDD to DRVSS1/2 −0.3 V to 4.5 V
IOVDD to DVSS −0.3 V to 3.9 V
Digital input voltage to DVSS −0.3 V to IOVDD + 0.3 V
Analog input (except VBAT) voltage to AVSS1/2 −0.3 V to AVDD + 0.3 V
VBAT input voltage to AVSS1/2 −0.3 V to 6 V
AVSS1/2 to DRVSS1/2 to DVSS −0.1 V to 0.1 V
AVDD1/2 to DRVDD −0.1 V to 0.1 V
Operating temperature range −40°C to 85°C
Storage temperature range −65°C to 105°C
Junction temperature (T
J
Max) 105°C
QFN package
Power dissipation (T
J
Max − T
A
)/θ
JA
QFN package
θ
JA
Thermal impedance (with thermal pad soldered to board) 27°C/W
Lead temperature Infrared (15 sec) 240°C
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
If the TSC2101 is used to drive high power levels to an 8-Ω load for extended intervals at an ambient temperature above 80°C, multiple vias should
be used to electrically and thermally connect the thermal pad on the QFN package to an internal heat dissipating ground plane on the user’s PCB.