Datasheet

TSC2101
SLAS392D JUNE 2003 REVISED MAY 2005
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20
D Left Justified Mode
In left-justified mode, the MSB of right channel is valid on the rising edge of BCLK, following the falling edge on
WCLK. Similarly the MSB of left channel is valid on the rising edge of BCLK following the rising edge of
WCLK.
BCLK
WCLK
SDIN/
SDOUT
n n1 1 0 n n1 1 0
1/fs
LSBMSB
Left Channel Right Channel
n n1n2 2 n2 2
Figure 16. Timing Diagram for Left-Justified Mode
D I
2
S Mode
In I
2
S mode, the MSB of left channel is valid on the second rising edge of BCLK, after the falling edge on
WCLK. Similarly the MSB of right channel is valid on the second rising edge of BCLK, after the rising edge of
WCLK.
BCLK
WCLK
SDIN/
SDOUT
n n1 1 0 n n1 1 0
1/fs
LSBMSB
Left Channel Right Channel
n
1 clock before MSB
n2 2 n2 2
Figure 17. Timing Diagram for I2S Mode
D DSP Mode
In DSP mode, the falling edge of WCLK starts the data transfer with the left channel data first and immediately
followed by the right channel data. Each data bit is valid on the falling edge of BCLK.
BCLK
WCLK
SDIN/
SDOUT
n n1 1 0 n n1 1 0
1/fs
LSBMSB
Left Channel Right Channel
n n11 0
MSB LSB
n2 2 n2 2 n2
MSBLSB
Figure 18. Timing Diagram for DSP Mode