Datasheet

TSC2101
SLAS392D JUNE 2003 REVISED MAY 2005
www.ti.com
13
th
(WS)
ts
(WS)
ts
(DI)
th
(DI)
td
(DOBCLK)
WCLK
BCLK
SDOUT
SDIN
tH(BCLK)
tL(BCLK)
tP(BCLK)
ts
(WS)
th
(WS)
Figure 4. DSP Timing in Slave Mode
Typical Timing Requirements (see Figure 4)
PARAMETER
(1)
IOVDD = 1.1 V IOVDD = 3.3 V
UNITS
PARAMETER
(1)
MIN MAX MIN MAX
UNITS
t
H
(BCLK) BCLK high period 40 35 ns
t
L
(BCLK) BCLK low period 40 35 ns
t
P
(BCLK) BCLK period 80 80 ns
t
s
(WS) WCLK setup 6 6 ns
t
h
(WS) WCLK hold 6 6 ns
t
d
(DOBCLK) BCLK to DOUT delay 30 15 ns
t
s
(DI) SDIN setup 6 6 ns
t
h
(DI) SDIN hold 6 6 ns
t
r
Rise time 5 4 ns
t
f
Fall time 5 4 ns
(1)
These parameters are based on characterization and are not tested in production.