Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - Touchscreen controller 12 Bit 1x TSC input VQFN 48

TSC2101

SLAS392D− JUNE 2003 − REVISED MAY 2005

AUDIO CODEC WITH INTEGRATED HEADPHONE, SPEAKER

AMPLIFIER AND TOUCH SCREEN CONTROLLER

FEATURES

D Stereo Audio Playback Up to 48 ksps

D Mono Audio Record up to 48 ksps

D Integrated PLL for Audio Clock Generation

D Programmable Gain Amplifiers

D Hardware Automatic Gain Control

D Programmable Digital Audio Effects

Processing

D Stereo Headset Interface

D Cellular Headset Interface

D 8-Ω Speaker Driver

D 32-Ω Receiver Driver

D Interface with Microphone

D Auto-Detection of Headset and Button Press

D Supports Both Cap and Cap-Less Interface

for Headset

D Programmable Audio Routing

D 4-Wire Touch Screen Interface

D Integrated Touch Screen Processor With

Fully Automated Modes of Operation

D Programmable Converter Resolution, Speed,

and Averaging

D Programmable Autonomous Timing Control

D Direct Battery Measurement

D Built-In Buffer for Touch Screen Data

D SPI™ Serial Interface

D Low Power

D Full Power-Down Control

D 48-Pin QFN Package

APPLICATIONS

D Personal Digital Assistants

D Smart Cellular Phones

D MP3 Players

DESCRIPTION

The TSC2101 is a low-power highly integrated high

performance codec and touch screen controller, which

supports stereo audio DAC, mono audio ADC and SAR

ADC.

The TSC2101 features a high-performance audio codec

with 16, 20, 24, or 32-bit stereo playback, mono record

functionality at up to 48 ksps. The device integrates

several analog features such as support for headset

interface, cellular headset interface, microphone interface,

and speaker and receiver drivers. The device supports

auto detection of headset and button press without any

glue logic. The TCS2101 has fully programmable audio.

The digital audio data format is programmable to work with

popular audio standard protocols (I2S, DSP, left/right

justified) in master or slave mode, and also includes an

on-chip PLL for flexible clock generation capability.

The TSC2101 contains a 12-bit 4-wire resistive touch

screen converter complete with drivers, and interfaces to

the host controller through a standard SPI™ serial

interface. The on-chip processor provides extensive

features specifically designed to reduce host processor

and bus overhead, with capabilities that include fully

automated operating modes, programmable conversion

resolution up to 12 bits, programmable sampling rates up

to 125 kHz, programmable conversion averaging, and

programmable on-chip timing generation.

The TSC2101 offers battery measurement inputs capable

of reading battery voltages up to 6 V, while operating at

only 3 V. It also has an on-chip temperature sensor

capable of reading 0.3°C resolution. The TSC2101 is

available in a 48-lead QFN.

US Patent No. 6246394

SPI is a trademark of Motorola.

PRODUCTION DATA information is current as of publication date. Products

conform to specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

www.ti.com

Summary of content (96 pages)

PAGE 1
TSC2101 www.ti.
PAGE 2
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
PAGE 3
TSC2101 www.ti.
PAGE 4
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 ELECTRICAL CHARACTERISTICS At +25°C, AVDD1, AVDD2, DRVDD, IOVDD = 3.3 V, BVDD = 3.9 V, DVDD = 1.8 V, Vref = 2.5 V, Fs (Audio) = 48 kHz, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNITS TOUCH SCREEN AUXILIARY ANALOG INPUT Input voltage range Input capacitance 0 AUX1/2 input selected as input by touch touch-screen screen Input leakage current +VREF V 25 pF ±1 µA BATTERY MONITOR INPUTS Input voltage range 0.
PAGE 5
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 ELECTRICAL CHARACTERISTICS (continued) At +25°C, AVDD1, AVDD2, DRVDD, IOVDD = 3.3 V, BVDD = 3.9 V, DVDD = 1.8 V, Int. Vref = 2.5 V, Fs (Audio) = 48 kHz, unless otherwise noted (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS MICIN_HED 1020 Hz sine wave input, Fs = 48 ksps MICROPHONE INPUT TO ADC Full-scale input voltage (0 dB) 0.707 Input common mode SNR Measured as idle channel noise, 0 dB gain, A-weighted THD 0.
PAGE 6
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 ELECTRICAL CHARACTERISTICS (continued) At +25°C, AVDD1, AVDD2, DRVDD, IOVDD = 3.3 V, BVDD = 3.9 V, DVDD = 1.8 V, Vref = 2.5 V, Fs (Audio) = 48 kHz, unless otherwise noted (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Load = 16 Ω (single-ended), 50 pF DAC HEADPHONE OUTPUT Full-scale output voltage (0dB) 0.848 Output common mode Vrms 1.
PAGE 7
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 ELECTRICAL CHARACTERISTICS (continued) At +25°C, AVDD1, AVDD2, DRVDD, IOVDD = 3.3 V, BVDD = 3.9 V, DVDD = 1.8 V, Vref = 2.5 V, Fs (Audio) = 48 kHz, unless otherwise noted (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 1020-Hz Sine wave input on CP_IN, Load on CP_IN TO 32Ω RECEIVER (SPK1−OUT32N) SPK1−OUT32N = 32 Ω (differential), 50 pF Full-scale input voltage (0 dB) 0.707 Input common mode Vrms 1.
PAGE 8
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 ELECTRICAL CHARACTERISTICS (continued) At +25°C, AVDD1, AVDD2, DRVDD, IOVDD = 3.3 V, BVDD = 3.9 V, DVDD = 1.8 V, Vref = 2.5 V, Fs (Audio) = 48 kHz, unless otherwise noted (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS POWER SUPPLY REQUIREMENTS Power supply voltage AVDD1, AVDD2 3 3.3 3.6 V DRVDD 3 3.3 3.6 V BVDD IOVDD Max MCLK = 100 MHz Max MCLK = 50 MHz DVDD 3 4.2 V 2 3.6 V 1.1 3.6 V 1.95 V 1.65 1.
PAGE 9
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 FUNCTIONAL BLOCK DIAGRAM AVDD1 Y+ X− X+ Y− Touch Panel Drivers VBAT Battery Monitor AVDD2 DRVDD BVDD DVDD IOVDD SCLK OSC SAR ADC Temperature Measurement VREF MICBIAS_HED MIC_DETECT_IN MICBIAS_HND Internal Reference 2.0/2.5/3.3 To Detection block MISO PINTDAV RESET 0 to 59.5dB (0.5dB steps) AUX1 AUX2 MICIN_HED 0 to 59.5dB (0.5dB steps) 12 to −34.5dB (0.
PAGE 10
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 SPI TIMING DIAGRAM /SS S SPISELZ S S SCLK S S SPISELZ S SPICLK MISO S E SPISELZ L t sck tLead twsck twsck tv MOSI tsu tr BIT 6 . . . 1 tdis LSB OUT thi MSB IN SPISELZ tf tho MSB OUT ta t td tLag BIT 6 . . . 1 LSB IN TYPICAL TIMING REQUIREMENTS All specifications typical at 25°C, DVDD = 1.8 V(1) PARAMETER IOVDD = 1.1 V MIN MAX IOVDD = 3.
PAGE 11
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 AUDIO INTERFACE TIMING DIAGRAMS WCLK td(WS) BCLK td(DO−WS) td(DO−BCLK) SDOUT th(DI) ts(DI) SDIN Figure 1. I2S/LJ/RJ in Master Mode Typical Timing Requirements (see Figure 1) IOVDD = 1.1 V PARAMETER(1) MIN MAX IOVDD = 3.
PAGE 12
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 WCLK th(WS) BCLK tL(BCLK) tH(BCLK) ts(WS) td(DO−WS) td(DO−BCLK) tP(BCLK) SDOUT th(DI) ts(DI) SDIN Figure 3. I2S/LJF/RJF Timing in Slave Mode Typical Timing Requirements (see Figure 3) PARAMETER(1) IOVDD = 1.1 V MIN MAX IOVDD = 3.
PAGE 13
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 WCLK th(WS) BCLK ts(WS) th(WS) tL(BCLK) tH(BCLK) ts(WS) td(DO−BCLK) tP(BCLK) SDOUT th(DI) ts(DI) SDIN Figure 4. DSP Timing in Slave Mode Typical Timing Requirements (see Figure 4) PARAMETER(1) IOVDD = 1.1 V MIN MAX IOVDD = 3.
PAGE 14
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 TYPICAL CHARACTERISTICS 1.5 AVDD1/AVDD2 = 3.3 V, TA = 25 C, IR = 2.5 V 1 LSB 0.5 0 −0.5 −1 −1.5 500 0 1000 1500 2000 CODE 2500 3000 3500 4000 Figure 5. SAR INL (TA = 25 C, Internal Reference = 2.5 V, 12 bit, AVDD1/AVDD2 = 3.3 V) 1 AVDD1/AVDD2 = 3.3 V, TA = 25 C, IR = 2.5 V LSB 0.5 0 −0.5 −1 0 500 1000 1500 2000 CODE 2500 3000 3500 4000 Figure 6. SAR DNL (TA = 25 C, Internal Reference = 2.5 V, 12 bit, AVDD1/AVDD2 = 3.
PAGE 15
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 0 AVDD1/AVDD2 = 3.3 V, TA = 25 C, −20 −40 dB −60 −80 −100 −120 −140 −160 500 0 1000 1500 2000 2500 3000 3500 4000 f − Frequency − Hz Figure 8. ADC FFT Plot at 8 ksps (TA = 25 C, −1 dB, 1 kHz input, AVDD1/AVDD2 = 3.3 V) 0 AVDD1/AVDD2 = 3.3 V, TA = 25 C, −20 −40 dB −60 −80 −100 −120 −140 −160 5000 0 10000 15000 f − Frequency − Hz 20000 Figure 9. ADC FFT Plot at 48 ksps (TA = 25 C, −1 dB, 1 kHz input, AVDD1/AVDD2 = 3.
PAGE 16
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 20 AVDD1/AVDD2 = 3.3 V, TA = 25 C, RL = 16 W 0 −20 dB −40 −60 −80 −100 −120 −140 −160 0 5000 10000 15000 20000 f − Frequency − Hz Figure 11. DAC FFT Plot (TA = 25 C, −1 dB, 1 kHz Input, AVDD1/AVDD2/DRVDD = 3.3 V, RL = 16 Ω) THD − Total Hormonic Distortion − dB −77 AVDD1/AVDD2 = 3.3 V, TA = 25 C, RL = 16 W −78 −79 −80 −81 −82 −83 −84 5 10 15 20 25 30 Power − mW 35 40 45 Figure 12.
PAGE 17
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 THD − Total Hormonic Distortion − dB −60 AVDD1/AVDD2/DRDD = 3.3 V, BVDD = 3.9 V TA = 25 C, RL = 8 W −65 −70 −75 −80 −85 −90 0 50 100 150 200 250 300 350 400 Power − mW Figure 13. THD vs Power on Loudspeaker Driver (TA = 25 C, 1 kHz Input, AVDD1/AVDD2/DRVDD = 3.3 V, BVDD = 3.9 V, RL = 8 Ω) 450 Max Power Output − mW 400 350 300 250 200 150 2.7 2.9 3.1 3.3 3.5 3.7 BVDD − V 3.9 4.1 Figure 14.
PAGE 18
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 OVERVIEW The TSC2101 is a highly integrated stereo audio DAC and mono audio ADC with touch screen controller for portable computing, communication and entertainment applications. A register-based architecture eases integration with microprocessor-based systems through a standard SPI bus. All peripheral functions are controlled through the registers and on-board state machines.
PAGE 19
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 D Word Select Signals The word select signal (WCLK) indicates the channel being transmitted: — WCLK = 0: left channel for I2S mode; — WCLK = 1: right channel for I2S mode. For other modes refer to the timing diagrams below. D Bitclock (BCLK) Signal In addition to being programmable as master or slave mode, the BCLK can also be configured in two transfer modes, 256-S transfer mode and continuous transfer mode, which are described below.
PAGE 20
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 D Left Justified Mode In left-justified mode, the MSB of right channel is valid on the rising edge of BCLK, following the falling edge on WCLK. Similarly the MSB of left channel is valid on the rising edge of BCLK following the rising edge of WCLK. 1/fs WCLK BCLK Left Channel SDIN/ SDOUT n n−1 n−2 2 Right Channel 1 0 MSB n n−1 n−2 2 1 0 n n−1 LSB Figure 16.
PAGE 21
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 AUDIO DATA CONVERTERS The TSC2101 includes a stereo audio DAC and a mono audio ADC. Both ADC and DAC can operate with a maximum sampling rate of 53 kHz and support all audio standard rates of 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, and 48 kHz.
PAGE 22
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 D When PLL is enabled Fsref + MCLK 2048 K P P = 1, 2, 3 … 8 K = J.D J = 1, 2, 3 ….64 D = 0, 1, 2 … 9999 P, J and D are register programmable. where J is integer part of K before the decimal point, and D is four-digit fractional part of K after the decimal point, including lagging zeros. Examples: If K = 8.5, then J = 8, D = 5000 If K = 7.12, then J = 7, D = 1200 If K = 7.
PAGE 23
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 MONO AUDIO ADC Analog Front End The analog front end of the audio ADC consists of an analog MUX and a programmable gain amplifier (PGA). The MUX can connect either of the Headset Input (MICIN_HED), Handset Input (MICIN_HND), AUX1 and AUX2 signal through the PGA to the ADC for audio recording. The Cell-phone Input (CP_IN) can also be connected to ADC through a PGA at the same time. This enables recording of conversation during a cell-phone call.
PAGE 24
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 Target gain represents the nominal output level at which the AGC attempts to hold the ADC output signal level. The TSC2101 allows programming of eight different target gains, which can be programmed from –5.5 dB to –24 dB relative to a full-scale signal. Since the TSC2101 reacts to the signal absolute average and not to peak levels, it is recommended that the target gain be set with enough margin to avoid clipping at the occurrence of loud sounds.
PAGE 25
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 Table 1.
PAGE 26
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 These coefficients implement a shelving filter with 0 dB gain from dc to approximately 150 Hz, at which point it rolls off to 3 dB attenuation for higher frequency signals, thus giving a 3-dB boost to signals below 150 Hz. The N and D coefficients are represented by 16−bit twos complement numbers with values ranging from –32768 to +32767. Frequency response plots are given in the Audio Codec Filter Frequency Responses section of this data sheet.
PAGE 27
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 DAC Powerdown The DAC powerdown flag (D4D3 of control register 05H/page 2) along with D10 of control register 05H/page 2 denotes the powerdown status of the DAC according to Table 2. Table 2. DAC Powerdown Status D10, D4, D3 POWERUP/POWERDOWN STATE OF DAC 0,0,0 DAC left and right are in stable powerup state. 0,0,1 DAC left is in stable powerup state. DAC right is in the process of powering up.
PAGE 28
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 0 −2 −4 Gain − dB −6 −8 −10 −12 −14 −16 −18 −20 0 200 400 600 f − Frequency − Hz 800 1000 Figure 20. Uncompensated Response For 16-Ω Load and 50-mF Decoupling Capacitor 0 −2 −4 Gain − dB −6 −8 −10 −12 −14 −16 −18 −20 0 200 400 600 f − Frequency − Hz 800 1000 Figure 21.
PAGE 29
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 For the cap interface, this feature can be disabled by setting bit D0 of control register 20H/page 2. In the case of the cap-less interface, VGND short circuit protection must also be disabled, which can be achieved by setting bit D4 of control register 21H/page 2. The TSC2101 implements a pop reduction scheme to reduce audible artifacts during powerup and powerdown of headphone drivers.
PAGE 30
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 MICBIAS_HND 2.5 MICIN_HND OUT8P LOUDSPEAKER OUT8N MICBIAS_HED MIC_DETECT_IN Stereo Cellular g g s m s g m 3.3V To Detection block MICIN_HED s OUT32N Stereo + Cellular −1 s s RECEIVER −1 SPK1 SPK2 m = mic s = stere g = ground/midbias SPKFC VGND Figure 22. Connection Diagram for Capless Interface D Cap Interface Figure 23 shows connection diagram to device for cap interface. 30 To Detection block 1.
PAGE 31
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 MICBIAS_HND 2.5V MICIN_HND LOUDSPEAKER OUT8P OUT8N MICBIAS_HED MIC_DETECT_IN Stereo Cellular Stereo + Cellular g g s m s m 2.5V To Detection block MICIN_HED s RECEIVER g −1 s s m = mic s = stere g = ground/midbias OUT32N −1 SPK1 SPK2 SPKFC VGND To Detection block 1.5 V Figure 23.
PAGE 32
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 s s s g g g s s m m Stereo + Cellular g m s s Cellular g m s Stereo g s s Figure 24. Connection Diagram for Jacks D Headset Detection − Interrupt polarity: Active high. − Typical interrupt duration: 1.75 ms.
PAGE 33
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 Analog Mixer The analog mixer can be used to route the analog input selected for the ADC through an analog volume control and then mix it with the audio DAC output. The analog mixer feature is available only if the single ended microphone input or the AUX input is selected as the input to the ADC, not when the ADC input is configured in fully-differential mode. This feature is available even if the ADC and DAC are powered down.
PAGE 34
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 Measuring touch pressure (Z) can also be done with the TSC2101. To determine pen or finger touch, the pressure of the touch needs to be determined. Generally, it is not necessary to have very high performance for this test; therefore, the 8-bit resolution mode is recommended (however, calculations are shown with the 12-bit resolution mode). There are several different ways of performing this measurement. The TSC2101 supports two methods.
PAGE 35
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 The ADC is controlled by an ADC control register. Several modes of operation are possible, depending upon the bits set in the control register. Channel selection, scan operation, averaging, resolution, and conversion rate may all be programmed through this register. These modes are outlined in the sections below for each type of analog input. The results of conversions made are stored in the appropriate result register.
PAGE 36
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 The internal reference voltage should only be used in the single-ended mode for battery monitoring, temperature measurement, and for utilizing the auxiliary inputs. Optimal touch-screen performance is achieved when using a ratiometric conversion, thus all touch-screen measurements are done automatically in the ratiometric mode. An external reference can also be applied to the VREF pin, and the internal reference can be turned off.
PAGE 37
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 AVDD1 DATAV PINTDAV 50 kΩ TEMP1 Y+ TEMP2 HIGH EXCEPT WHEN TEMP1. TEMP2 ACTIVATED TEMP DIODE X+ Y− ON Y+ or X+ DRIVERS ON OR TEMP1 , TEMP2 MEASUREMENTS ACTIVATED Figure 28. PINTDAV Functional Block Diagram In modes where the TSC2101 needs to detect if the screen is still touched (for example, when doing a PINTDAV initiated X, Y, and Z conversion), the TSC2101 must reset the drivers so that the 50 KΩ resistor is connected.
PAGE 38
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 Table 4. Programmable PINTDAV Functionality D15−D14 PINTDAV FUNCTION 00 Acts as PEN interrupt (active low) only. When PEN touch is detected, PINTDAV goes low. 01 Acts as data available (active low) only. The PINTDAV goes low as soon as one set of ADC conversions are completed for data of X,Y, XYZ, battery input, or auxiliary input selected by D13−D10 in control register 00H/Page 1.
PAGE 39
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 Temperature Measurement In some applications, such as battery charging, a measurement of ambient temperature is required. The temperature measurement technique used in the TSC2101 relies on the characteristics of a semiconductor junction operating at a fixed current level. The forward diode voltage (VBE) has a well-defined characteristic versus temperature.
PAGE 40
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 0.20 Error in Measurement − °C 0 −0.20 −0.40 −0.60 −0.80 −1 −1.20 −40 −20 0 20 40 60 TA − Free-Air Temperature − C 80 100 Figure 31. Typical Plot of Single Measurement Method After Calibrating for Offset and Gain At Two Temperatures The second mode uses a two-measurement (differential) method. This mode requires a second conversion with a current 82 times larger.
PAGE 41
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 4 Error in Measurement − °C 3 2 1 0 −1 −2 −3 −4 −40 −20 0 20 40 60 TA − Free-Air Temperature − C 80 100 Figure 32. Typical Plot of Differential Measurement Method After Calibrating for Offset at Room Temperature The TSC2101 supports programmable auto-temperature measurement mode, which can be enabled using control register 0CH/page 1. In this mode, the TSC2101 can auto-start the temperature measurement after a programmable interval.
PAGE 42
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 LDO or DC-DC Converter Battery 0.5 to 6 V 3.0 V to 3.6 V + − VDD R VBAT ADC 8 kΩ 2 kΩ Figure 33. Battery Measurement Functional Block Diagram Battery measurement can only be done in host−controlled mode. See the section Conversion Time Calculation for the TSC2101 and subsection Non Touch Measurement Operation in this data sheet for timing diagrams and conversion time calculations.
PAGE 43
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 Where: VREF is the SAR ADC reference Vsar is input to the SAR ADC The TSC2101 supports programmable auto−auxiliary measurement mode, which can be enabled using control register 0CH/page 1. In this mode, the TSC2101 can auto start the auxiliary measurement after a programmable interval. The user can program minimum and maximum threshold values through a register.
PAGE 44
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 Converted data is automatically written into the FIFO. To control the writing, reading and interrupt process, a write pointer (WRPTR), a read pointer (RDPTR) and a trigger pointer (TGPTR) are used. The read pointer always shows the location, which will be read next. The write pointer indicates the location, in which the next converted data is going to be written.
PAGE 45
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 SPI Digital Interface All TSC2101 control registers are programmed through a standard SPI bus. The SPI allows full-duplex, synchronous, serial communication between a host processor (the master) and peripheral devices (slaves). The SPI master generates the synchronizing clock and initiates transmissions. The SPI slave devices depend on a master to start and synchronize transmissions. A transmission begins when initiated by a master SPI.
PAGE 46
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 BIT 15 MSB BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 LSB R/W* PG3 PG2 PG1 PG0 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 0 0 0 0 0 Figure 36. TSC2101 Command Word SS SCLK MOSI COMMAND WORD DATA DATA Figure 37. Register Write Operation SS SCLK MOSI COMMAND WORD MOSO DATA DATA Figure 38.
PAGE 47
TSC2101 www.ti.
PAGE 48
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 X, Y, Z1, Z2, BAT, AUX1, AUX2, TEMP1 and TEMP2 Registers The results of all ADC conversions are placed in the appropriate data register.
PAGE 49
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 BIT NAME RESET VALUE READ/ WRITE D7−D6 ADAVG 00 R/W FUNCTION Converter Averaging Control. These two bits allow user to specify the number of averages the converter will perform selected by bit D0, which selects either Mean Filter or Median Filter.
PAGE 50
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 BIT NAME RESET VALUE READ/ WRITE D10 XSTAT 0 R FUNCTION X Data Register Status 0 => No new data is available in X−data register 1 => New data for X−coordinate is available in register Note: This bit gets cleared only after the converted data of X coordinate has been completely read out of the register. This bit is not valid in case of buffer mode.
PAGE 51
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 REGISTER 02H: Buffer Control BIT NAME RESET VALUE READ/ WRITE D15 BUFRES 0 R/W Buffer Reset. 0 => Buffer mode is disabled and RDPTR, WRPTR & TGPTR set to their reset value. 1 => Buffer mode is enabled. D14 BUFCONT 0 R/W Buffer Mode Selection 0 => Continuous conversion mode. 1 => Single shot mode.
PAGE 52
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 REGISTER 04H: Reset Control BIT NAME RESET VALUE READ/ WRITE D15−D0 RSALL R/W FFFFH FUNCTION Reset All. Writing the code 0xBB00, as shown below, to this register causes the TSC2101 to reset all its control registers to their default, power−up values. 1011101100000000 => Reset all control registers Others => Do not write other sequences to the register.
PAGE 53
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 REGISTER 07H: Temperature Min Threshold Measurement BIT NAME D15−D13 RESET VALUE READ/ WRITE FUNCTION 0’s R D12 TMNES 0 R/W Reserved Min Temperature (TEMP1 or TEMP2) threshold check enable for Auto/Non−Auto−Scan Measurement. 0 => Min Temperature threshold check is disabled. 1 => Min Temperature threshold check is enabled. Only valid for TEMP1 or TEMP2.
PAGE 54
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 REGISTER 0CH: Measurement Configuration BIT NAME RESET VALUE READ/ WRITE D15 TSCAN 0 R/W TEMP Configuration when Auto−Temperature is selected 0 => TEMP1 is used for auto−temperature function 1 => TEMP2 is used for auto−temperature function D15 A1CONF 0 R/W AUX1 Configuration. 0 => AUX1 is used for voltage measurement. 1 => AUX1 is used for resistance measurement. D14 A2CONF 0 R/W AUX2 Configuration.
PAGE 55
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 REGISTER 0DH: Programmable Delay In-Between Continuous Conversion BIT NAME D15 NTSPDELE N D14−D12 NTSPDINTV RESET VALUE READ/ WRITE 0 R/W Programmable delay for non−touch screen auto measurement mode 0 => Programmable delay is disabled for non−touch screen auto measurement mode. 1 => Programmable delay is enabled for non−touch screen auto measurement mode.
PAGE 56
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 PAGE 2 CONTROL REGISTER MAP REGISTER 00H: Audio Control 1 BIT NAME RESET VALUE READ/ WRITE D15−D14 ADCHPF 00 R/W D13−D12 FUNCTION ADC High Pass Filter 00 => Disabled 01 => −3db point = 0.0045xFs 10 => −3dB point = 0.0125xFs 11 => −3dB point = 0.
PAGE 57
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 REGISTER 01H: Gain Control for Headset/Aux Input BIT NAME RESET VALUE READ/ WRITE D15 ADMUT_HED 1 R/W Headset/Aux Input Mute 1 => Headset/Aux Input Mute 0 => Headset/Aux Input not muted Note: If AGC is enabled and Headset/Aux Input is selected then ADMUT_HED+ADPGA_HED reflects gain being applied by AGC. D14−D8 ADPGA_HED 1111111 R/W ADC Headset/Aux PGA Settings 0000000 => 0 dB 0000001 => 0.5 dB 0000010 => 1.0 dB ……… 1110110 => 59.0 dB ..
PAGE 58
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 REGISTER 02H: CODEC DAC Gain Control BIT NAME RESET VALUE READ/ WRITE D15 DALMU 1 R/W DAC Left Channel Mute 1 => DAC Left Channel Muted 0 => DAC Left Channel not muted D14−D8 DALVL 1111111 R/W DAC Left Channel Volume Control 0000000 => DAC left channel volume = 0 dB 0000001 => DAC left channel volume = −0.5 dB ….. 1111110 => DAC left channel volume = −63.0 dB 1111111 => DAC left channel volume = −63.
PAGE 59
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 REGISTER 04H: Audio Control 2 BIT NAME RESET VALUE READ/ WRITE D15 KCLEN 0 R/W Keyclick Enable 0 => Keyclick Disabled 1 => Keyclick Enabled Note: This bit is automatically cleared after giving out the keyclick signal length equal to the programmed value. D14−D12 KCLAC 100 R/W Keyclick Amplitude Control 000 => Lowest Amplitude …. 100 => Medium Amplitude ….
PAGE 60
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 BIT NAME RESET VALUE READ/ WRITE D1 DASTC 0 R/W D0 ADGAF 0 R FUNCTION DAC Channel PGA Soft−stepping control 0 => 0.5 dB change every WCLK 1 => 0.5 dB change every 2 WCLK Headset/Aux or Handset PGA Flag 1 => Gain applied = PGA register setting. 0 => Gain applied ≠ PGA Register setting Note: This flag indicates when the soft−stepping for PGA is completed.
PAGE 61
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 BIT NAME RESET VALUE READ/WRITE D1 EFFCTL 0 R/W Digital Audio Effects Filter 0 => Disable digital audio effects filter 1 => Enable digital audio effects filter FUNCTION D0 DEEMPF 0 R/W De−emphasis Filter Enable 0 => Disable de−emphasis filter 1 => Enable de−emphasis filter NOTE: D15−D6 are all 1’s, then full codec section is powered down.
PAGE 62
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 REGISTER 09H: Digital Audio Effects Filter Coefficients BIT NAME RESET VALUE (IN DECIMAL) READ/ WRITE D15−D0 L_N2 26461 R/W FUNCTION Left channel bass-boost coefficient N2. REGISTER 0AH: Digital Audio Effects Filter Coefficients BIT NAME RESET VALUE (IN DECIMAL) READ/ WRITE D15−D0 L_N3 27619 R/W FUNCTION Left channel bass-boost coefficient N3.
PAGE 63
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 REGISTER 15H: Digital Audio Effects Filter Coefficients BIT NAME RESET VALUE (IN DECIMAL) READ/ WRITE D15−D0 R_N4 −27034 R/W FUNCTION Right channel bass-boost coefficient N4. REGISTER 16H: Digital Audio Effects Filter Coefficients BIT NAME RESET VALUE (IN DECIMAL) READ/ WRITE D15−D0 R_N5 26461 R/W FUNCTION Right channel bass-boost coefficient N5.
PAGE 64
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 D7−D2 J_VAL D1−D0 000001 R/W 00 R J value: Valid when PLL is enabled 000000 => Not valid, 000001 => 1, 000010 => 2, 000011 => 3, …….. 111100 => 60, 111101 => 61, 111110 => 62, 111111 => 63 Reserved (Write only 00) REGISTER ICH: PLL Programmability BIT NAME RESET VALUE READ/WRITE D15−D2 D_VAL 0 (decimal) R/W D1−D0 Reserved 0 R FUNCTION D value: Valid when PLL is enabled D value is valid from 0000 to 9999 in decimal.
PAGE 65
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 REGISTER 1EH: Gain Control for Handset Input BIT NAME RESET VALUE READ/WRITE D15 ADMUT_HND 1 R/W Handset Input Mute 1 => Handset Input Mute 0 => Handset Input not muted Note: If AGC is enabled and handset Input is selected then ADMUT_HND+ADPGA_HND will reflect gain being applied by AGC. FUNCTION D14−D8 ADPGA_HND 1111111 R/W D7−D5 AGCTG_HND 000 R/W ADC Handset PGA Settings 0000000 => 0 dB 0000001 => 0.5 dB 0000010 => 1.0 dB ....
PAGE 66
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 REGISTER 1FH: Gain Control for Cell Phone Input and Buzzer Input BIT NAME RESET VALUE READ/WRITE D15 MUT_CP 1 R/W Cell phone Input PGA Power−down 1 => Power−down cell-phone input PGA 0 => Power−up cell phone input PGA FUNCTION D14−D8 CPGA 1000101 R/W Cell−phone Input PGA Settings. 0000000 => −34.5 dB 0000001 => −34 dB 0000010 => −33.5 dB ... 1000101 => 0 dB 1000110 => 0.5 dB ... 1011100 => 11.
PAGE 67
TSC2101 www.ti.
PAGE 68
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 REGISTER 21H: Audio Control 6 BIT NAME RESET VALUE READ/ WRITE D15 SPL2LSK 0 R/W Routing Selected for SPK1 Goes to OUT8P−OUT8N (Loudspeaker) Also. 0 => None of the routing selected for SPK1 goes to OUT8P−OUT8N. 1 => Routing selected for SPK1 using D14−D9 of control register 20H/page 2 goes to OUT8P−OUT8N. Note: This programming is valid only if SPK1/OUT32N and SPK2 are powered down.
PAGE 69
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 REGISTER 22H: Audio Control 7 BIT NAME RESET VALUE READ/ WRITE D15 DETECT 0 R/W D14−D13 HESTYPE 00 R Type of Headset Detected. 00 => No headset detected. 01 => Stereo headset detected. 10 => Cellular headset detected 11 => Stereo+cellular headset detected Note: These two bits are valid only if the headset detection is enabled. D12 HDDETFL 0 R Headset Detection Flag. 0 => Headset is not detected 1 => Headset is detected.
PAGE 70
TSC2101 www.ti.
PAGE 71
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 BIT NAME RESET VALUE READ/ WRITE D7−D5 AGCTG_CELL 000 R/W AGC Target Gain for Cell−phone Input. These three bits set the AGC’s targeted ADC output level. 000 => −5.5 dB 001 => −8.0 dB 010 => −10 dB 011 => −12 dB 100 => −14 dB 101 => −17 dB 110 => −20 dB 111 => −24 dB D4−D1 AGCTC_CELL 0000 R/W AGC Time Constant for Cell Input. These four bits set the AGC attack and decay time constants.
PAGE 72
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 BIT NAME RESET VALUE D9−D6 READ/ WRITE FUNCTION 0000 R D5 PSEQ 0 R/W Disable Drivers (SPK1/SPK2/OUT32N/VGND) Pop Sequencing 0 => Enable drivers pop sequencing 1 => Disable drivers pop sequencing D4 PSTIME 0 R/W Drivers (SPK1/SPK2) Pop Sequencing Duration in Cap Mode 0 => 802 ms. 1 => 4006 ms.
PAGE 73
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 REGISTER 27H: Cell-Phone AGC Control BIT NAME RESET VALUE READ/ WRITE D15−D9 CMPGA 1111111 R/W D8−D6 CDEBNS 000 R De−bounce Time for Transition from Normal Mode to Silence Mode (Input Level is Below Noise Threshold Programmed by AGCNL). This is Valid for Cell−phone AGC. 000 => 0 ms 001 => 0.5 ms 010 => 1.0 ms 011 => 2.0 ms 100 => 4.0 ms 101 => 8.0 ms 110 => 16.0 ms 111 => 32.
PAGE 74
TSC2101 www.ti.
PAGE 75
TSC2101 www.ti.
PAGE 76
TSC2101 www.ti.
PAGE 77
TSC2101 www.ti.
PAGE 78
TSC2101 www.ti.
PAGE 79
TSC2101 www.ti.
PAGE 80
TSC2101 www.ti.
PAGE 81
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 Port Scan Operation The time needed to complete one set of port scan conversions is given by: t coordinate +3 Ǌ ƪǒ N AVG N BITS Ǔ )1 ƫ ǋ 8 MHz ) n ) 12 ) 1 1 ƒ conv t OSC ) 31 t OSC ) n2 t OSC where: n1 = 6 ; if ƒconv = 8 MHz 7 ; if ƒconv ≠ 8 MHz n2 = 0 ; if external reference mode is selected 3 ; if tREF = 0 µs or reference is programmed for power up all the time.
PAGE 82
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 Figure 40. Frequency Response of ADC High-Pass Filter (Fcutoff = 0.0045 Fs) Figure 41. Frequency Response of ADC High-Pass Filter (Fcutoff = 0.
PAGE 83
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 Figure 42. Frequency Response of ADC High-Pass Filter (Fcutoff = 0.025 Fs) DAC CHANNEL DIGITAL FILTER FREQUENCY RESPONSES Figure 43.
PAGE 84
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 Figure 44. DAC Channel Digital Filter Pass-Band Frequency Response Figure 45.
PAGE 85
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 Figure 46. De-Emphasis Filter Response at 32 Ksps Figure 47.
PAGE 86
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 Figure 48. De-Emphasis Filter Frequency Response at 44.1 Ksps Figure 49. De-Emphasis Error at 44.
PAGE 87
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 Figure 50. De-Emphasis Frequency Response at 48 Ksps Figure 51.
PAGE 88
TSC2101 www.ti.com SLAS392D− JUNE 2003 − REVISED MAY 2005 PLL PROGRAMMING The on-chip PLL in the TSC2101 can be used to generate sampling clocks from a wide range of MCLK’s available in a system. The PLL works by generating oversampled clocks with respect to Fsref (44.1 kHz or 48 kHz). Frequency division generates all other internal clocks. Table 7 and Table 8 gives a sample programming for PLL registers for some standard MCLK’s when PLL is required.
PAGE 89
PACKAGE OPTION ADDENDUM www.ti.
PAGE 90
PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PAGE 91
PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TSC2101IRGZR Package Package Pins Type Drawing VQFN RGZ 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 7.3 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 7.3 1.5 12.0 16.
PAGE 92
PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TSC2101IRGZR VQFN RGZ 48 2500 336.6 336.6 28.
PAGE 93
PAGE 94
PAGE 95
PAGE 96
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.