Datasheet

Program Description
3-23
Operation
Figure 3−12. Base Boost Filter Screen at Default
3.5.4.1 Interface Section
This section (refer to Figure 3−10) controls the behavior of the I
2
S port (BCLK,
LRCLK, DIN, and DOUT pins). In this EVM, the audio port transfers the 16 bit
data in I
2
S format, and the codec reference sample rate is at 44.1 kHz.
The TSC2101 is programmed as a slave by default. The onboard processor
TAS1020B is the master, which generates the BCLK and LRCLK signal.
If the TSC2101 is used as a master, the onboard processor should be disabled
and the I
2
S port should be detached from the processor by turning OFF the
onboard I
2
S interface. Refer to the previous chapter for the hardware settings.
3.5.4.2 PLL Section
There is an on-chip phase-locked loop (PLL) on the audio codec part of the
TSC2101. The PLL can be enabled or disabled, based on the given master
clock (MCLK) to the TSC2101 and the required reference frequency (FSref)
for the codec. For more details on the PLL, refer to the TSC2101 data sheet.
The PLL can be set on the PLL Secton of Audio 1 screen (Figure 3−10).
With the EVM board, the MCLK is at 11.2896 MHz, and the reference sample
rate is at 44.1 kHz by default.