Datasheet

Program Description
3-16
Figure 3−7. Configuration Screen With External Reference Selection
3.5.3.3 Audio PLL Section
On the audio codec part of the TSC2100, there is an on-chip phase-lock-loop
(PLL). The PLL can be enabled or disabled, based on the given master clock
(MCLK) to the TSC2100 and the required reference frequency (FSref) for the
codec. For more details on the PLL, refer to the TSC2100 data sheet.
With the EVM board, the MCLK is at 11.2896 MHz, and the codec sample rate
is also fixed at 44.1 kHz. So no PLL is necessary.
With the TSC2100EVM, changing the PLL setting may cause audio
distortions.