Datasheet

Program Description
3-14
3.5.3 Configuration Screen
This screen provides access to all of the configurable settings for the
TSC2100’s A/D converter and reference, as shown in Figure 3−6.
Located on the right hand side of the screen are the programmable phase lock
loop (PLL) settings, which are not the A/D settings but the audio settings.
Figure 3−6. Configuration Screen
3.5.3.1 ADC Control Section
This section controls all of the parameters of the A/D converter. Each slider
controls one parameter, whose value is shown next to the slider. Each slider
is described below.
J Resolution
Selects between 8-, 10-, and 12-bit resolution.
J Conversion Clock
The internal clock which runs the A/D converter can run at 8, 4, 2, or 1 MHz.
When running at 8 MHz, only 8-bit resolution is possible; when running at
4 MHz, 8- or 10-bit resolution is possible, but 12-bit is not. These restric-
tions are reflected in the operation of this program, since only 1- or 2-MHz
clock rates allow 12-bit resolution to be chosen.