Datasheet

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SBAS265G − OCTOBER 2002 − REVISED JANUARY 2008
www.ti.com
18
+V
CC
S 2.7V, +V
CC
S IOVDD S 1.5V, C
LOAD
= 50pF
SYMBOL DESCRIPTION
MIN TYP MAX
UNITS
t
ACQ
Acquisition Time 1.5 µs
t
DS
DIN Valid Prior to DCLK Rising 100 ns
t
DH
DIN Hold After DCLK High 50 ns
t
DO
DCLK Falling to DOUT Valid 200 ns
t
DV
CS Falling to DOUT Enabled 200 ns
t
TR
CS Rising to DOUT Disabled 200 ns
t
CSS
CS Falling to First DCLK Rising 100 ns
t
CSH
CS Rising to DCLK Ignored 10 ns
t
CH
DCLK High 200 ns
t
CL
DCLK Low 200 ns
t
BD
DCLK Falling to BUSY Rising/Falling 200 ns
t
BDV
CS Falling to BUSY Enabled 200 ns
t
BTR
CS Rising to BUSY Disabled 200 ns
Table 6. Timing Specifications, T
A
= −405C to +855C
1
DCLK
CS
11DOUT
BUSY
A2SDIN A1 A0
MODE
SER/
DFR
PD1 PD0
109876543210 11 10 9 8 7
A1 A0
15 1 15
Power−Down
1
A2SA1A0
MODE
PD1 PD0 A2S
SER/
DFR
Figure 13. Maximum Conversion Rate, 15 Clocks-per-Conversion
Data Format
The TSC2046 output data is in Straight Binary format, as
shown in Figure 14. This figure shows the ideal output
code for the given input voltage and does not include the
effects of offset, gain, or noise.
8-Bit Conversion
The TSC2046 provides an 8-bit conversion mode that can
be used when faster throughput is needed and the digital
result is not as critical. By switching to the 8-bit mode, a
conversion is complete four clock cycles earlier. Not only
does this shorten each conversion by four bits (25% faster
throughput), but each conversion can actually occur at a
faster clock rate. This is because the internal settling time
of the TSC2046 is not as critical—settling to better than 8
bits is all that is needed. The clock rate can be as much as
50% faster. The faster clock rate and fewer clock cycles
combine to provide a 2x increase in conversion rate.
Output Code
0V
FS = Full−Scale Voltage = V
REF
(1)
1LSB = V
REF
(1)
/4096
FS
−
1LSB
11...111
11...110
11...101
00...010
00...001
00...000
1LSB
NOTES:
Input Voltage
(2)
(V)
(1) Reference voltage at converter: +REF
−
(
−
REF); see Figure 2.
(2) Input voltage at converter, after multiplexer: +IN
−
(
−
IN); see
Figure 2.
Figure 14. Ideal Input Voltages and Output Codes