Datasheet

t
HD, STA
t
SU, DAT
t
HD, DAT
t
SU, STA
t
SU, STO
t
HD, STA
t
LOW
t
HIGH
t
R
t
F
t
BUF
SDA
START
CONDITION
START
CONDITION
STOP
CONDITION
REPEATED
START
CONDITION
SCL
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SBAS472 –DECEMBER 2009 www.ti.com
TIMING INFORMATION
Figure 1. Detailed I/O Timing
TIMING REQUIREMENTS
All specifications typical at –40°C to +85°C, V
DD
= 1.6V, unless otherwise noted.
2-WIRE STANDARD MODE PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
Reset low time t
WL(RESET)
3.6V ≥ VDD ≥ 1.6V 200 ns
TIMING REQUIREMENTS: I
2
C Standard Mode (SCL = 100kHz)
All specifications typical at –40°C to +85°C, V
DD
= 1.6V, unless otherwise noted.
TWO-WIRE STANDARD MODE PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
SCL clock frequency f
SCL
0 100 kHz
Bus free time between a STOP and START condition t
BUF
4.7 μs
Hold time (repeated) START condition t
HD, STA
4.0 μs
Low period of SCL clock t
LOW
4.7 μs
High period of the SCL clock t
HIGH
4.0 μs
Setup time for a repeated START condition t
SU, STA
4.7 μs
Data hold time t
HD, DAT
0 3.45 μs
Data setup time t
SU, DAT
250 ns
Rise time for both SDA and SCL signals (receiving) t
R
C
b
= total bus capacitance 1000 ns
Fall time for both SDA and SCL signals (receiving) t
F
C
b
= total bus capacitance 300 ns
Fall time for both SDA and SCL signals (transmitting) t
F
C
b
= total bus capacitance 250 ns
Setup time for STOP condition t
SU, STO
4.0 μs
Capacitive load for each bus line C
b
C
b
= total capacitance of one bus line in pF 400 pF
8 bits 40 SCL + 127 CCLK, V
DD
= 1.8V 434.7 μs
Cycle time
12 bits 49 SCL + 148 CCLK, V
DD
= 1.8V 570.9 μs
8 bits V
DD
= 1.8V 2.3 kSPS
Effective throughput
12 bits V
DD
= 1.8V 1.75 kSPS
8 bits V
DD
= 1.8V 16.1 kHz
Equivalent rate = effective throughput × 7
12 bits V
DD
= 1.8V 12.26 kHz
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