Datasheet
C lumnso
(FRONTVIEW)
A CB D
GND
A0 RESET
VDD/REF
Y-Y+X+
3
2
1
SCL
PENIRQ
SDA
AUX
Rows
X-
TSC2017
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SBAS472 –DECEMBER 2009
PIN CONFIGURATIONS
YZG PACKAGE
WCSP-12
(TOP VIEW, SOLDER BUMPS ON BOTTOM SIDE)
PIN ASSIGNMENTS
NO. NAME I/O A/D DESCRIPTION
A1 AUX I A Auxiliary channel input
A2 VDD/REF Supply voltage and external reference input
A3 X+ I A X+ channel input
B1 PENIRQ O D Data available interrupt output. A delayed (process delay) pen touch detect. Pin polarity with active low.
B2 A0 I D Address input bit 0
B3 Y+ I A Y+ channel input
C1 SDA I/O D Serial data I/O
C2 RESET I D External hardware-reset input
C3 X– I A X– channel input
Serial clock. This pin is normally an input, but acts as an output when the device stretches the clock to delay a bus
D1 SCL I/O D
transfer.
D2 GND Ground
D3 Y– I A Y– channel input
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