Datasheet

TIMING REQUIREMENTS
(1)
TSC2008
www.ti.com .......................................................................................................................................................... SBAS406B – JUNE 2008 – REVISED MARCH 2009
All specifications typical at – 40 ° C to +85 ° C, VDD = 1.6V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN MAX UNIT
1.2V ≤ VDD < 1.6V, 40% to 60% duty cycle 182 ns
t
C(SCLK)
SPI serial clock cycle time 1.6 ≤ VDD < 2.7V, 40% to 60% duty cycle 62.5 ns
2.7V ≤ VDD ≤ 3.6V, 40% to 60% duty cycle 40 ns
1.2V ≤ VDD < 1.6V, 10pF load 5.5 MHz
f
SCLK
SPI serial clock frequency 1.6 ≤ VDD < 2.7V, 10pF load 16 MHz
2.7V ≤ VDD ≤ 3.6V, 10pF load 25 MHz
t
WH(SCLK)
SPI serial clock high time 0.4 × t
C(SCLK)
0.6 × t
C(SCLK)
ns
t
WL(SCLK)
SPI serial clock low time 0.4 × t
C(SCLK)
0.6 × t
C(SCLK)
ns
1.2V ≤ VDD < 1.6V 22 ns
t
SU(CSF-SCLK1R)
Enable lead time
1.6 ≤ VDD < 3.6V 14 ns
1.2V ≤ VDD < 1.6V 55 ns
t
D(CSF-SDOVALID)
Slave access time
1.6 ≤ VDD < 3.6V 25 ns
1.2V ≤ VDD < 1.6V 40 80 ns
t
H(SCLKF-SDOVALID)
MISO data hold time
1.6 ≤ VDD < 3.6V 6 30 ns
1.2V ≤ VDD < 1.6V 50 ns
t
WH(CS)
Sequential transfer delay
1.6 ≤ VDD < 3.6V 20 ns
1.2V ≤ VDD < 1.6V 25 ns
t
SU(SDI-SCLKR)
MOSI data setup time
1.6 ≤ VDD < 3.6V 10 ns
t
H(SDI-SCLKR)
MOSI data hold time 5 ns
1.2V ≤ VDD < 1.6V 55 ns
t
DIS(CSR-SDOZ)
Slave MISO disable time
1.6 ≤ VDD < 3.6V 25 ns
1.2V ≤ VDD < 1.6V 50 ns
t
SU(SCLKF-CSR)
Enable lag time
1.6 ≤ VDD < 3.6V 20 ns
1.2V ≤ VDD < 1.6V 55 ns
PENIRQ (used as BUSY)
t
D(SCLKR-PENIRQF)
delay from SCLK rising edge
1.6 ≤ VDD < 3.6V 25 ns
Setup time from PENIRQ 1.2V ≤ VDD < 1.6V 50 ns
t
SU(PENIRQR-SCLKR)
(used as BUSY) to the rising
1.6 ≤ VDD < 3.6V 20 ns
edge of SCLK
t
D(RESET)
Reset period requirement 200 ns
t
R
Rise time VDD = 3V, f
SCLK
= 25MHz 3 ns
t
F
Fall time VDD = 3V, f
SCLK
= 25MHz 3 ns
(1) All input signals are specified with t
R
= t
F
= 5ns (10% to 90% of VDD) and timed from a voltage level of (V
IL
+ V
IH
)/2.
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