Datasheet
TSC2008
SBAS406B – JUNE 2008 – REVISED MARCH 2009 ..........................................................................................................................................................
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
At T
A
= – 40 ° C to +85 ° C, V
DD
= +1.2V to +3.6V, unless otherwise noted.
TSC2008
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUT/OUTPUT
Logic family CMOS
V
IH
1.2V ≤ V
DD
< 3.6V 0.7 × V
DD
V
DD
+ 0.3 V
1.2V ≤ V
DD
< 1.6V – 0.3 0.2 × V
DD
V
V
IL
1.6V ≤ V
DD
≤ 3.6V – 0.3 0.3 × V
DD
V
I
IL
CS, SCLK, and SDI pins – 1 1 µ A
Logic level C
IN
CS, SCLK, and SDI pins 10 pF
V
OH
I
OH
= 2 TTL loads V
DD
– 0.2 V
DD
V
V
OL
I
OL
= 2 TTL loads 0 0.2 V
I
LEAK
Floating output – 1 1 µ A
C
OUT
Floating output 10 pF
Data format Straight Binary
POWER SUPPLY REQUIREMENTS
Power-supply voltage
V
DD
Specified performance 1.2 3.6 V
12-bit, 69.6k eq rate
(5)
285.0 320.0 µ A
f
SCLK
= 5MHz,
V
DD
= 1.2V
f
ADC
= 2MHz,
8.2k eq rate
(5)
30.4 37.7 µ A
PD[1:0] = 0,0
Quiescent supply current
82.6k eq rate
(5)
344.0 425.0 µ A
(V
DD
with sensor off)
V
DD
= 1.8V
12-bit,
8.2k eq rate
(5)
34.5 42.2 µ A
f
SCLK
= 10MHz,
f
ADC
= 2MHz,
84.8k eq rate
(5)
461.0 570.0 µ A
PD[1:0] = 0,0
V
DD
= 2.7V
8.2k eq rate
(5)
44.6 55.1 µ A
Power-down supply current CS = 1, SDI = SCLK = 1, PENIRQ = 1, PD[1:0] = 0,0 0 0.8 µ A
POWER ON/OFF SLOPE REQUIREMENTS (see Figure 37 )
t
VDD_OFF_RAMP
T
A
= – 40 ° C to +85 ° C 2 kV/s
T
A
= – 40 ° C to +85 ° C, VDD = 0V 1 s
t
VDD_OFF
T
A
= – 20 ° C to +85 ° C, VDD = 0V 0.3 s
t
VDD_ON_RAMP
T
A
= – 40 ° C to +85 ° C 12 kV/s
t
DEVICE_READY
T
A
= – 40 ° C to +85 ° C 2 ms
(5) See the Throughput Rate and SPI Bus Traffic section for calculation information.
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