Datasheet

8-BIT OPERATION TIMING
1
SCLK
CS
8 1
1 1
SDO
PENIRQ
SSDI
ControlBits
S
ControlBits
HIGH: Disableor(EnableandNotTouched)
New DefinitionPENIRQ
LOW: EnableandTouched
7 6 5 7 6 54 3 2 1 0
8 1 18
A2 A1 A0
MODE
SER/
DFR
PD1 PD0
A2 A1 A0
MODE
SER/
DFR
PD1 PD0
n n +1
n n +1
HIGH: Disableor
(EnableandNotTouched)
LOW: EnableandTouched
Idle
Acquire
Conv
Idle
Acquire
Conv
Idle
New DefPENIRQ
1
SCLK
CS
8 1
SDO
PENIRQ
SSDI
ControlBits
S
1 1
ControlBits
HIGH: Disableor(EnableandNotTouched)
LOW: EnableandTouched
7 6 5 7 6 5 44 3 2 1 0
8 1
A2 A1 A0
MODE
SER/
DFR
PD1 PD0
A2 A1 A0
MODE
SER/
DFR
PD1 PD0
n n +1
n n +1
HIGH: Disableor
(EnableandNotTouched)
LOW: EnableandTouched
Idle
Acquire
Conv
Idle
Acquire
Conv
Idle
TSC2008
www.ti.com .......................................................................................................................................................... SBAS406B – JUNE 2008 – REVISED MARCH 2009
If the 8-bit ADC mode produces an acceptable result, then 16 SCLKs per cycle operation can also be used, as
shown in Figure 32 . If SDO is released one-half SCLK cycle earlier (with the SDO adjusted option), the fastest
transfer (eight SCLKs per cycle) is achievable; see Figure 33 .
Figure 32. Conversion Timing — 8-Bit Mode, 16 SCLKs per Cycle, 8-Bit Bus Interface, without Adjusted
SDO Timing (TSC2046 -Compatible)
Figure 33. Conversion Timing — 8-Bit Mode, 8 SCLKs per Cycle, 8-Bit Bus Interface, with Adjusted SDO
Timing
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Product Folder Link(s): TSC2008