Datasheet

12-BIT OPERATION TIMING
t
ACQ
Idle
Acquire
Conv
10
Idle
1SCLK
CS
8 1
11SDO
Drivers1and2
(1)
(SER/DFRHigh)
Drivers1and2
(1, 2)
(SER/DFRLow)
(MSB)
(START)
(LSB)
A2S
On
On
Off Off
Off Off
SDI A1 A0
MODE
SER/
DFR
PD1 PD0
10 9 8 7 6 5 4 3 2 1 0 ZeroFilled...
8 1 8
NOTES:
(1)ForY-Position,Driver1isonX+isselected,andDriver2isoff.ForX-Position,Driver1isoff,Y+isselected,andDriver2ison.Y willturnon-
whenpower-downmodeisenteredandPD0=0.
(2)DriverswillremainonifPD0=1(nopowerdown)untilselectedinputchannel,orpower ishigh.-downmodeischanged,or CS
PENIRQ
HIGH: Disableor(EnableandNotTouched)
New DefinitionPENIRQ
LOW: EnableandTouched
HIGH: Disableor
(EnableandNotTouched)
LOW: EnableandTouched
1
SCLK
CS
8 1
SDO
PENIRQ
SSDI
ControlBits
S
ControlBits
HIGH: Disableor(EnableandNotTouched)
NewPENIRQDefinition
LOW: EnableandTouched
8 1 18
11 10 9 8 7 6 5 4 3 2 1 0 11 10 9
A2
1 1
A1 A0
MODE
SER/
DFR
PD1 PD0
A2 A1 A0
MODE
SER/
DFR
PD1 PD0
n n +1
n n +1
HIGH: Disableor
(EnableandNotTouched)
LOW: EnableandTouched
Idle
Acquire
Conv
Idle
Acquire
Conv
Idle
TSC2008
SBAS406B – JUNE 2008 – REVISED MARCH 2009 .......................................................................................................................................................... www.ti.com
A single touch result can be easily achieved using 24 SCLKs per cycle operation when the 12-bit ADC mode is
used, as shown in Figure 30 . However, because this operation uses slightly more bus bandwidth, a more efficient
method is to overlap the control bytes with the conversion result using 16 SCLKs per cycle operation; see
Figure 31 .
Figure 30. Conversion Timing — 12-Bit Mode, 24 SCLKs per Cycle, 8-Bit Bus Interface
The control bits for conversion n + 1 can be overlapped with conversion n to allow for a conversion every 16
clock cycles, as shown in Figure 31 . After submitting the control bits, the TSC2008 uses the internal clock to
acquire data from seven conversions (see Figure 28 ). Deselecting the TSC2008 ( CS = '1') during this time period
allows the host to communicate with the other peripherals using the same SPI bus before reading out the ADC
data.
Figure 31. Conversion Timing — 12-Bit Mode, 16 SCLKs per Cycle, 8-Bit Bus Interface, with Earliest Start
of New Command
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