Datasheet

TSC2007
SBAS405A – MARCH 2007 – REVISED MARCH 2009 ...................................................................................................................................................... www.ti.com
TIMING REQUIREMENTS: I
2
C High-Speed Mode (SCL = 3.4MHz)
All specifications typical at – 40 ° C to +85 ° C, V
DD
= 1.6V, unless otherwise noted.
2-WIRE HIGH-SPEED MODE PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
SCL clock frequency f
SCL
0 3.4 MHz
Hold time (repeated) START condition t
HD, STA
160 ns
Low period of SCL clock t
LOW
160 ns
High period of the SCL clock t
HIGH
60 ns
Setup time for a repeated START condition t
SU, STA
160 ns
Data hold time t
HD, DAT
0 70 ns
Data setup time t
SU, DAT
10 ns
Rise time for SCL signal (receiving) t
R
C
b
= total bus capacitance 10 40 ns
Rise time for SDA signal (receiving) t
R
C
b
= total bus capacitance 10 80 ns
Fall time for SCL signal (receiving) t
F
C
b
= total bus capacitance 10 40 ns
Fall time for SDA signal (receiving) t
F
C
b
= total bus capacitance 10 80 ns
Fall time for both SDA and SCL signals (transmitting) t
F
C
b
= total bus capacitance 10 80 ns
Setup time for STOP condition t
SU, STO
160 ns
Capacitive load for each bus line C
b
C
b
= total capacitance of one bus line in pF 100 pF
8 bits 40 SCL + 127 CCLK, V
DD
= 1.8V 46.5 µ s
Cycle time
12 bits 49 SCL + 148 CCLK, V
DD
= 1.8V 95.3 µ s
8 bits V
DD
= 1.8V 21.52 kSPS
Effective throughput
12 bits V
DD
= 1.8V 10.49 kSPS
8 bits V
DD
= 1.8V 150.65 kHz
Equivalent rate = effective throughput × 7
12 bits V
DD
= 1.8V 73.46 kHz
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