Datasheet
TIMING REQUIREMENTS: I
2
C Fast Mode (SCL = 400kHz)
TSC2007
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...................................................................................................................................................... SBAS405A – MARCH 2007 – REVISED MARCH 2009
All specifications typical at – 40 ° C to +85 ° C, V
DD
= 1.6V, unless otherwise noted.
2-WIRE FAST MODE PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
SCL clock frequency f
SCL
0 400 kHz
Bus free time between a STOP and START condition t
BUF
1.3 µ s
Hold time (repeated) START condition t
HD, STA
0.6 µ s
Low period of SCL clock t
LOW
1.3 µ s
High period of the SCL clock t
HIGH
0.6 µ s
Setup time for a repeated START condition t
SU, STA
0.6 µ s
Data hold time t
HD, DAT
0 0.9 µ s
Data setup time t
SU, DAT
100 ns
Rise time for both SDA and SCL signals (receiving) t
R
C
b
= total bus capacitance 20+0.1 × C
b
300 ns
Fall time for both SDA and SCL signals (receiving) t
F
C
b
= total bus capacitance 20+0.1 × C
b
300 ns
Fall time for both SDA and SCL signals (transmitting) t
F
C
b
= total bus capacitance 20+0.1 × C
b
250 ns
Setup time for STOP condition t
SU, STO
0.6 µ s
Capacitive load for each bus line C
b
C
b
= total capacitance of one bus line in pF 400 pF
8 bits 40 SCL + 127 CCLK, V
DD
= 1.8V 134.7 µ s
Cycle time
12 bits 49 SCL + 148 CCLK, V
DD
= 1.8V 203.4 µ s
8 bits V
DD
= 1.8V 7.42 kSPS
Effective throughput
12 bits V
DD
= 1.8V 4.92 kSPS
8 bits V
DD
= 1.8V 51.97 kHz
Equivalent rate = effective throughput × 7
12 bits V
DD
= 1.8V 34.42 kHz
TIMING REQUIREMENTS: I
2
C High-Speed Mode (SCL = 1.7MHz)
All specifications typical at – 40 ° C to +85 ° C, V
DD
= 1.6V, unless otherwise noted.
2-WIRE HIGH-SPEED MODE PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
SCL clock frequency f
SCL
0 1.7 MHz
Hold time (repeated) START condition t
HD, STA
160 ns
Low period of SCL clock t
LOW
320 ns
High period of the SCL clock t
HIGH
120 ns
Setup time for a repeated START condition t
SU, STA
160 ns
Data hold time t
HD, DAT
0 150 ns
Data setup time t
SU, DAT
10 ns
Rise time for SCL signal (receiving) t
R
C
b
= total bus capacitance 20 80 ns
Rise time for SDA signal (receiving) t
R
C
b
= total bus capacitance 20 160 ns
Fall time for SCL signal (receiving) t
F
C
b
= total bus capacitance 20 80 ns
Fall time for SDA signal (receiving) t
F
C
b
= total bus capacitance 20 160 ns
Fall time for both SDA and SCL signals (transmitting) t
F
C
b
= total bus capacitance 20 160 ns
Setup time for STOP condition t
SU, STO
160 ns
Capacitive load for each bus line C
b
C
b
= total capacitance of one bus line in pF 400 pF
8 bits 40 SCL + 127 CCLK, V
DD
= 1.8V 58.2 µ s
Cycle time
12 bits 49 SCL + 148 CCLK, V
DD
= 1.8V 109.7 µ s
8 bits V
DD
= 1.8V 17.17 kSPS
Effective throughput
12 bits V
DD
= 1.8V 9.12 kSPS
8 bits V
DD
= 1.8V 120.22 kHz
Equivalent rate = effective throughput × 7
12 bits V
DD
= 1.8V 63.81 kHz
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