Datasheet
THROUGHPUT RATE AND I
2
C BUS TRAFFIC
12-Bit Operation
8-Bit Operation
TSC2007
SBAS405A – MARCH 2007 – REVISED MARCH 2009 ......................................................................................................................................................
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Although the internal A/D converter has a sample rate of up to 200kSPS, the throughput presented at the bus is
much lower. The rate is reduced because preprocessing manages the redundant work of filtering out noise. The
throughput is further limited by the I
2
C bus bandwidth. The effective throughput is approximately 20kSPS at 8-bit
resolution, or 10kSPS at 12-bit resolution. This preprocessing saves a large portion of the I
2
C bandwidth for the
system to use on other devices.
Each sample and conversion takes 19 CCLK cycles (12-bit), or 16 CCLK cycles (8-bit). For a typical internal
4MHz OSC clock, the frequency actually ranges from 3.66MHz to 3.82MHz. For V
DD
= 1.2V, the frequency
reduces to 3.19MHz, which gives a 3.19MHz/16 = 199kSPS raw A/D converter sample rate.
For 12-bit operation, sending the conversion result across the I
2
C bus takes 49 bus clocks (SCL clock). Each
write cycle takes 20 I
2
C cycles (START, STOP, address byte, 2 ACKs, and command byte). Each read cycle
takes 29 I
2
C cycles (START, STOP, address byte, 3 ACKs, and data bytes 1 and 2). Seven
sample-and-conversions take 19 x 7 internal clocks to complete. The MAV filter loop requires 19 internal clocks.
For V
DD
= 1.2V, the complete processed data cycle time calculations are shown in Table 5 . Because the first
acquisition cycle overlaps with the I/O cycle, four CCLKs should be deducted from the total CCLK cycles. For
12-bit mode, (19 × 7 + 19) – 4 = 148 CCLKs plus I/O are required.
For 8-bit operation, sending the conversion result across the I
2
C bus takes 40 bus clocks (SCL clock). Each write
cycle takes 20 I
2
C cycles (START, STOP, address byte, 2 ACKs, and command byte). Each read cycle takes 20
I
2
C cycles (START, STOP, address byte, 2 ACKs, and data byte 1). Seven sample-and-conversions takes 16 x 7
internal clocks to complete. The MAV filter loop requires 19 internal clocks. For V
DD
= 1.2V, the complete
processed data cycle time calculations are shown in Table 5 . Because the first acquisition cycle overlaps with the
I/O cycle, four CCLKs should be deducted from the total CCLK cycles. For 8-bit mode, (16 × 7 + 19) – 4 = 127
CCLKs plus I/O are required.
Table 5. Measurement Cycle Time Calculations
STANDARD MODE: 100kHz (Period = 10 µ s)
8-Bit 40 × 10 µ s + 127 × 313ns = 439.8 µ s (2.27kSPS through the I
2
C bus)
12-Bit 49 × 10 µ s + 148 × 625ns = 582.5 µ s (1.72kSPS through the I
2
C bus)
FAST MODE: 400kHz (Period = 2.5 µ s)
8-Bit 40 × 2.5 µ s + 127 × 313ns = 139.8 µ s (7.15kSPS through the I
2
C bus)
12-Bit 49 × 2.5 µ s + 148 × 625ns = 215 µ s (4.65kSPS through the I
2
C bus)
HIGH-SPEED MODE: 1.7MHz (Period = 588ns)
8-Bit 40 × 588ns + 127 × 313ns = 63.3 µ s (15.79kSPS through the I
2
C bus)
12-Bit 49 × 588ns + 148 × 625ns = 121.3 µ s (8.24kSPS through the I
2
C bus)
HIGH-SPEED MODE: 3.4MHz (Period = 294ns)
8-Bit 40 × 294ns + 127 × 313ns = 51.6 µ s (19.39kSPS through the I
2
C bus)
12-Bit 49 × 294ns + 148 × 625ns = 106.9 µ s (9.35kSPS through the I
2
C bus)
As an example, use V
DD
= 1.2V and 12-bit mode with the Fast-mode I
2
C clock (f
SCL
= 400kHz). The equivalent
TSC throughput is at least seven times faster than the effective throughput across the bus (4.65k x 7 =
32.55kSPS). The supply current to the TSC for this rate and configuration is 128 µ A. To achieve an equivalent
sample throughput of 8.2kSPS using the device without preprocessing, the TSC2007 consumes only (8.2/32.55)
× 128 µ A = 32.24 µ A.
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