Datasheet

READ A CONVERSION/READ CYCLE
SDA
SCL
1
0 0
1 0 A1
A0
R/W
1
0
D11 D10 D9 D8 D7 D6 D5 D4
0
D3 D2 D1 D0
0 00 0 1
START TSC2007
ACK
MASTER
ACK
MASTER
NACK
STOPor
Repeated
START
AddressByte
DataByte1
DataByte2
TSC2007
www.ti.com ...................................................................................................................................................... SBAS405A – MARCH 2007 – REVISED MARCH 2009
For best performance, the I
2
C bus should remain in an idle state while an A/D conversion is taking place. This
idling prevents digital clock noise from affecting the bit decisions being made by the TSC2007. The master
should wait for at least 10 µ s before attempting to read data from the TSC2007 to realize this best performance.
However, the master does not need to wait for a completed conversion before beginning a read from the slave, if
full 12-bit performance is not necessary.
Data access begins with the master issuing a START condition followed by the address byte (see Table 1 ) with
R/ W = 1.
When the eighth bit has been received and the address matches, the slave issues an acknowledge. The first
byte of serial data then follows (D11-D4, MSB first).
After the first byte has been sent by the slave, it releases the SDA line for the master to issue an acknowledge.
The slave responds with the second byte of serial data upon receiving the acknowledge from the master (D3-D0,
followed by four 0 bits). The second byte is followed by a NOT acknowledge bit (ACK = 1) from the master to
indicate that the last data byte has been received. If the master somehow acknowledges the second data byte,
invalid data are returned (FFh). This condition applies to both 12-and 8-bit modes. See Figure 32 for a complete
I
2
C read transmission.
Figure 32. Complete I
2
C Serial Read Transmission
Copyright © 2007 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): TSC2007