Datasheet

Touch Screen Settling
Variable Resolution
8-Bit Conversion
Conversion Clock and Conversion Time
Data Format
OutputCode
0V
FS=Full-ScaleVoltage=V
REF
(1)
1LSB=V /4096
REF
(1)
FS 1LSB-
11...111
11...110
11...101
00...010
00...001
00...000
1LSB
InputVoltage (V)
(2)
TSC2007
SBAS405A – MARCH 2007 – REVISED MARCH 2009 ...................................................................................................................................................... www.ti.com
In some applications, external capacitors may be required across the touch screen to filter noise picked up by the
touch screen (that is, noise generated by the LCD panel or backlight circuitry). These capacitors provide a
low-pass filter to reduce the noise, but they also cause a settling time requirement when the panel is touched.
The settling time typically shows up as a gain error. The problem is that the input and/or reference has not
settled to its final steady-state value before the A/D converter samples the input(s) and provides the digital
output. Additionally, the reference voltage may continue to change during the measurement cycle.
To resolve these settling-time problems, the TSC2007 can be commanded to turn on the drivers only without
performing a conversion (see Table 3 ). Time can then be allowed, before the command is issued, to perform a
conversion. Generally, the time it takes to communicate the conversion command over the I
2
C bus is adequate
for the touch screen to settle.
The TSC2007 provides either 8-bit or 12-bit resolution for the A/D converter. Lower resolution is often practical
for measuring slow changing signals such as touch pressure. Performing the conversions at lower resolution
reduces the amount of time it takes for the A/D converter to complete its conversion process, which also lowers
power consumption.
The TSC2007 provides an 8-bit conversion mode (M = 1) that can be used when faster throughput is needed,
and the digital result is not as critical (for example, measuring pressure). By switching to the 8-bit mode, a
conversion result can be read by transferring only one data byte. The internal clock runs twice as fast at 4MHz.
The faster clock shortens each conversion by four bits and reduces data transfer time, which results in fewer
clock cycles and provides lower power consumption.
The TSC2007 contains an internal clock, which drives the state machines inside the device that perform the
many functions of the part. This clock is divided down to provide a clock that runs the A/D converter. The
frequency of this clock is 4MHz clock for 8-bit mode, and 2MHz for the 12-bit mode.
The TSC2007 output data are in straight binary format as shown in Figure 26 . This figure shows the ideal output
code for the given input voltage and does not include the effects of offset, gain, or noise.
(1) Reference voltage at converter: +REF – ( – REF). See Figure 23 .
(2) Input voltage at converter, after multiplexer: +IN – ( – IN). See Figure 23 .
Figure 26. Ideal Input Voltages and Output Codes
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