Datasheet

TIMING INFORMATION
BIT0
t
DIS(CSR-SDOZ)
t
H(SDI-SCLKR)
NOTE: CPOL=0,CPHA=0,Byte0cyclerequires24SCLKs,andByte1cyclerequireseightSCLKs.
t
H(SCLKF-SDOVALID)
t
SU(SDI-SCLKR)
t
D(CSF-SDOVALID)
t
SU(SCLKF-CSR)
t
WH(CS)
t
C(SCLK)
t
SU(CSF-SCLK1R)
t
F
t
R
t
WL(SCLK)
t
WH(SCLK)
BIT1
MSBIN
MSBOUT
CS SS( )
SCLK
SDO(MISO)
SDI(MOSI)
BIT0BIT1
TIMING REQUIREMENTS
(1)
TSC2006
SBAS415C – JUNE 2007 – REVISED MARCH 2009 ......................................................................................................................................................... www.ti.com
The TSC2006 supports SPI programming in mode CPOL = 0 and CPHA = 0. The falling edge of SCLK is used to
change output (MISO) data and the rising edge is used to latch input (MOSI) data. Eight SCLKs are required to
complete the Byte 1 command cycle, and 24 SCLKs are required for the Byte 0 command cycle. CS can stay low
during the entire 24 SCLKs of a Byte 0 command cycle, or multiple mixed cycles of reading and writing of bytes
and register accesses, as long as the corresponding addresses are supplied.
Figure 1. Detailed I/O Timing
All specifications typical at – 40 ° C to +85 ° C, SNSVDD = I/OVDD = 1.6V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN MAX UNIT
SNSVDD ≥ 1.6V 10 µ s
t
WL(RESET)
(2)
Reset low time
1.2V ≤ SNSVDD < 1.6V 13 µ s
SNSVDD = I/OVDD ≥ 2.7V and ≤ 3.6V,
40 ns
40% to 60% duty cycle
SNSVDD = I/OVDD ≥ 1.6V and < 2.7V,
t
C(SCLK)
SPI serial clock cycle time 100 ns
40% to 60% duty cycle
SNSVDD = I/OVDD = 1.2V
182 ns
40% to 60% duty cycle
SNSVDD = I/OVDD ≥ 2.7V and ≤ 3.6V,
25 MHz
10pF load
f
SCLK
SPI serial clock frequency SNSVDD = I/OVDD ≥ 1.6V and < 2.7V,
10 MHz
10pF load
SNSVDD = I/OVDD = 1.2V, 10pF load 5.5 MHz
t
WH(SCLK)
SPI serial clock high time 0.4 × t
C(SCLK)
0.6 × t
C(SCLK)
ns
t
WL(SCLK)
SPI serial clock low time 0.4 × t
C(SCLK)
0.6 × t
C(SCLK)
ns
t
SU(CSF-SCLK1R)
Enable lead time 30 ns
t
D(CSF-SDOVALID)
Slave access time 15 ns
t
H(SCLKF-SDOVALID)
MISO data hold time 6 13 ns
t
WH(CS)
Sequential transfer delay 15 ns
t
SU(SDI-SCLKR)
MOSI data setup time 4 ns
t
H(SDI-SCLKR)
MOSI data hold time 4 ns
t
DIS(CSR-SDOZ)
Slave MISO disable time 15 ns
t
SU(SCLKF-CSR)
Enable lag time 30 ns
t
R
Rise time SNSVDD = I/OVDD = 3V, f
SCLK
= 25MHz 3 ns
t
F
Fall time SNSVDD = I/OVDD = 3V, f
SCLK
= 25MHz 3 ns
(1) All input signals are specified with t
R
= t
F
= 5ns (10% to 90% of I/OVDD) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2) Refer to Figure 34 .
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